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參數(shù)資料
| 型號(hào)： | VDP3104B |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Video Processor Family |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP64 |
| 封裝： | SHRINK, PLASTIC, DIP-64 |
| 文件頁(yè)數(shù)： | 38/72頁(yè) |
| 文件大?。?/td> | 603K |
| 代理商： | VDP3104B |
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VDP 31xxB
PRELIMINARY DATA SHEET
38
Micronas
Name
Default
Function
Mode
Number
of bits
I
2
C sub
address
OUTPUT PINS
h
’
10
8
w/r
output pin configuration
bit [2:0]
pin driver strength, MSY and CSY
7 = tristate
6 = minimum strength
0 = maximum strength
bit [4:3]
reserved (set to 0)
bit [5]
0/1
disable/enable internal resistor for
vertical and East/West drive output
bit [7:6]
function of CSY pin :
00
composite sync signal output
01
25 Hz output (field1/field2 signal)
10
no interlace (field 2), output = 0
11
1 MHz horizontal drive clock
0
PSTSY
VEWXR
CSYM
MISCELLANEOUS
h
’
32
8
w/r
fast blank interface mode
bit [0]
0
1
bit [1]
0/1
bit [2]
0/1
internal fast blank 1 from FBLIN1 pin
force internal fast blank 1 signal to high
internal fast blank active high/low
disable/enable clamping reference for
RGB outputs
full line MADC measurement window,
disables bit [3] in address h
’
25
horizontal flyback input active high/low
reserved (set to 0)
internal fast blank 1 from FBLIN1 pin
force internal fast blank 1 signal to low
bit [3]
1
bit [4]
bit [6:5]
bit [7]
0/1
0
1
0
FBMOD
FBFOH1
FBPOL
CLMPR
FLMW
FLPOL
FBFOL1
h
’
31
8
w/r
fast blank interface mode 2
bit [0]
0
1
bit [1]
0
1
bit [2]
0
1
bit [3]
0
1
bit [4]
0
1
bit [5]
0
1
bit [6]
0/1
bit [7]
internal fast blank 2 from FBLIN2 pin
force internal fast blank 2 signal to high
internal fast blank 2 from FBLIN2 pin
force internal fast blank 2 signal to low
fast blank input priority
FBLIN1 > FBLIN2
FBLIN1 < FBLIN2
fast blank monitor input select
monitor connected to FBLIN1 pin
monitor connected to FBLIN2 pin
half contrast switch enable
PORT0 enable / HCS disable
PORT0 disable / HCS enable
half contrast from HCS pin
force half contrast signal to high
half contrast active high/low at HCS pin
reserved (set to 0)
0
FBMOD2
FBFOH2
FBFOL2
FBPRIO
FBMON
HCSEN
HCSFOH
HCSPOL
h
’
34
16
w/r
IO Port
bit [6:0]
bit [7]
data to/from PORT[6:0]
front sync output at PORT1
PORT1 input/output enable
FSY output enable
port direction
switch PORT[bit
–
8] to input
switch PORT[bit
–
8] to output
port enable
COLOR[4:0] enable / PORT[6:2] disable
COLOR[4:0] disable / PORT[6:2] enable
0
1
bit [14:8]
0
1
bit [15]
0
1
0
IOPORT
IODATA
FSYOEN
IODIR
IOEN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VDP3108 | Single-Chip Video Processor |
| VDP3130Y | Video Processor Family |
| VDP31XXB | Video Processor Family |
| VDP3108PR | Consumer IC |
| VDSGLD_38.88 | TRANS PREBIASED PNP 200MW SOT23 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VDP3108 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Single-Chip Video Processor |
| VDP3108B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
| VDP3108PR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
| VDP3112B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
| VDP3116B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
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