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參數(shù)資料
| 型號： | VDP3104B |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | Video Processor Family |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP64 |
| 封裝： | SHRINK, PLASTIC, DIP-64 |
| 文件頁數(shù)： | 14/72頁 |
| 文件大小： | 603K |
| 代理商： | VDP3104B |
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VDP 31xxB
PRELIMINARY DATA SHEET
14
Micronas
2.7. Video Sync Processing
Fig. 2
–
11 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above 1 MHz. The sync is sep-
arated by a slicer; the sync phase is measured. A vari-
able window can be selected to improve the noise immu-
nity of the slicer. The phase comparator measures the
falling edge of sync, as well as the integrated sync pulse.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it thus
counts synchronously to the video signal.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/minimum
of the video signal. This information is processed by the
FP and used for gain control and clamping.
For vertical sync separation, the sliced video signal is in-
tegrated. The FP uses the integrator value to derive ver-
tical sync and field information.
The information extracted by the video sync processing
is multiplexed onto the hardware front sync signal (FSY)
and is distributed to the rest of the video processing sys-
tem. The format of the front sync signal is given in
Fig. 2
–
12.
The data for the vertical deflection, the sawtooth, and the
East-West correction signal is calculated by the
VDP 31xxB. The data is buffered in a FIFO and trans-
ferred to the back-end by a single wire interface.
Frequency and phase characteristics of the analog vid-
eo signal are derived from PLL1. The results are fed to
the scaler unit for data interpolation and orthogonaliza-
tion and to the clock synthesizer for line-locked clock
generation. Horizontal and vertical syncs are latched
with the line-locked clock.
phase
comparator
&
lowpass
counter
front-end
timing
front sync
skew
vblank
field
lowpass
1 MHz
&
syncslicer
horizontal
sync
separation
vertical
sync
separation
FIFO
Sawtooth
Parabola
Calculation
video
input
front
sync
generator
vertical
serial
data
vertical
E/W
sawtooth
clamping, colorkey, FIFO_write
PLL1
clamp &
signal
meas.
Fig. 2
–
11:
Sync separation block diagram
clock
synthesizer
syncs
clock
H/V syncs
F1
(not in scale)
input
analog
video
FSY
F1
Parity
V: vertical sync
0 = off
1 = on
F: field #
0 = field 1
1 = field 2
Fig. 2
–
12:
Front sync format
F0
skew
LSB
skew
MSB
not
F
V
F0 reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VDP3108 | Single-Chip Video Processor |
| VDP3130Y | Video Processor Family |
| VDP31XXB | Video Processor Family |
| VDP3108PR | Consumer IC |
| VDSGLD_38.88 | TRANS PREBIASED PNP 200MW SOT23 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VDP3108 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Single-Chip Video Processor |
| VDP3108B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
| VDP3108PR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Consumer IC |
| VDP3112B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
| VDP3116B | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Video Processor Family |
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