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參數資料
| 型號： | VDP3104B |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | Video Processor Family |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP64 |
| 封裝： | SHRINK, PLASTIC, DIP-64 |
| 文件頁數： | 30/72頁 |
| 文件大小： | 603K |
| 代理商： | VDP3104B |
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VDP 31xxB
PRELIMINARY DATA SHEET
30
Micronas
3. Serial Interface
3.1. I
2
C-Bus Interface
Communication between the VDP and the external con-
troller is done via I
2
C-bus. The VDP has two I
2
C-bus
slave interfaces (for compatibility with VPC/DDP ap-
plications)
–
one in the front-end and one in the back-
end. Both I
2
C-bus interfaces use I
2
C clock synchroniza-
tion to slow down the interface if required. Both I
2
C-bus
interfaces use one level of subaddress: the I
2
C-bus chip
address is used to address the IC and a subaddress se-
lects one of the internal registers. The I
2
C-bus chip ad-
dresses are given below:
Chip
Address
A6
A5
A4
A3
A2
A1
A0
R/W
front-end
1
0
0
0
1
1
1
1/0
back-end
1
0
0
0
1
0
1
1/0
The registers of the VDP have 8 or 16-bit data size;
16-bit registers are accessed by reading/writing two
8-bit data words.
Figure 3
–
1 shows I
2
C-bus protocols for read and write
operations of the interface; the read operation requires
an extra start condition and repetition of the chip address
with read command set.
3.2. Control and Status Registers
Table 3
–
1 gives definitions of the VDP control and status
registers. The number of bits indicated for each register
in the table is the number of bits implemented in hard-
ware, i.e. a 9-bit register must always be accessed using
two data bytes but the 7 MSB will be
‘
don
’
t care
’
on write
operations and
‘
0
’
on read operations. Write registers
that can be read back are indicated in Table 3
–
1.
Functions implemented by software in the on-chip con-
trol microprocessor (FP) are explained in Table 3
–
3.
A hardware reset initializes all control registers to 0. The
automatic chip initialization loads a selected set of regis-
ters with the default values given in Table 3
–
1.
The register modes given in Table 3
–
1 are
–
w:
write only register
–
w/r:
write/read data register
–
r:
read data from VDP
–
v:
register is latched with vertical sync
–
h:
register is latched with horizontal sync
The mnemonics used in the Micronas VDP demo soft-
ware are given in the last column.
W
P
1 or 2 byte Data
W
high byte Data
S
S
Ack
Ack
Ack
Ack
0111 1100
0111 1100
R
S
Ack
SDA
SCL
1
0
S
P
P
low byte Data
Ack
W
R
Ack
Nak
S
P
=
=
=
=
=
=
0
1
0
1
Start
Stop
Ack
Nak
Fig. 3
–
1:
I
2
C-bus protocols
1000 111
1000 111
1000 111
I
2
C write access
subaddress 7c
I
2
C read access
subaddress 7c
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