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參數(shù)資料
| 型號： | V63C31321024 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 32K X 32 CMOS Synchronous Burst Pipelined SRAM(32Kx32CMOS同步脈沖流水線式SRAM) |
| 中文描述： | 32K的× 32的CMOS SRAM的同步突發(fā)流水線（32Kx32CMOS同步脈沖流水線式的SRAM） |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 119K |
| 代理商： | V63C31321024 |
8
V63C31321024 Rev. 0.3 February 1999
MOSEL V ITELIC
V63C31321024
AC Test Loads and Waveform
AC Timing Characteristics
(V
CC
= 3.3V
±
5%, T
A
= 0 to 70
°
C)
#
Sym
Parameter
5
6
7
8
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
1
t
AS
Address Setup Time
2.5
–
2.5
–
2.5
–
2.5
–
ns
2
t
AH
Address Hold Time
0.5
–
0.5
–
0.5
–
0.5
–
ns
3
t
DS
Data Setup Time
2.5
–
2.5
–
2.5
–
2.5
–
ns
4
t
DH
Data Hold Time
0.5
–
0.5
–
0.5
–
0.5
–
ns
5
t
ADVS
ADV Setup Time
2.5
–
2.5
–
2.5
–
2.5
–
ns
6
t
ADVH
ADV Hold Time
0.5
–
0.5
–
0.5
–
0.5
–
ns
7
t
ADSS
ADSP Setup Time
2.5
–
2.5
–
2.5
–
2.5
–
ns
8
t
ADSH
ADSP Hold Time
0.5
–
0.5
–
0.5
–
0.5
–
ns
9
t
ADCS
ADSC Setup Time
2.5
–
2.5
–
2.5
–
2.5
–
ns
10
t
ADCH
ADSC Hold Time
0.5
–
0.5
–
0.5
–
0.5
–
ns
11
t
CES
CE1, CE2, CE3 Setup Time
2.5
–
2.5
–
2.5
–
2.5
–
ns
12
t
CEH
CE1, CE2, CE3 Hold Time
0.5
–
0.5
–
0.5
–
0.5
–
ns
13
t
WS
GW, BWE X Setup Time
2.5
–
2.5
–
2.5
–
2.5
–
ns
14
t
WH
GW, BWE X Hold Time
0.5
–
0.5
–
0.5
–
0.5
–
ns
15
t
CYC
Clock Cycle Time
10
–
11.1
–
13.3
–
15
–
ns
16
t
KH
Clock High Pulse Width
5
–
6
–
6
–
6
–
ns
17
t
KL
Clock Low Pulse Width
5
–
6
–
6
–
6
–
ns
18
t
KQ
Clock to Output Valid
–
5
–
6
–
7
–
8
ns
19
t
KHZ
Clock to Output High-Z
2
10
2
11.1
2
13.3
2
15
ns
1
20
t
KLZ
Clock to Output Low-Z
0
–
0
–
0
–
0
–
ns
1
21
t
KX
Clock to Output Invalid
2
–
2
–
2
–
2
–
ns
1
22
t
OE
Output Enable to Output Valid
–
5
–
6
–
7
–
8
ns
23
t
OHZ
Output Enable to Output High-Z
–
5
–
6
–
7
–
8
ns
1
50 ohm
1.5V
3.0V
0V
90%
10%
2 ns
I/O Pin
30 pF
Zo = 50 ohm
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