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參數(shù)資料
| 型號(hào)： | V63C31321024 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 32K X 32 CMOS Synchronous Burst Pipelined SRAM(32Kx32CMOS同步脈沖流水線式SRAM) |
| 中文描述： | 32K的× 32的CMOS SRAM的同步突發(fā)流水線（32Kx32CMOS同步脈沖流水線式的SRAM） |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 119K |
| 代理商： | V63C31321024 |
MOSEL V ITELIC
V63C31321024
4
V63C31321024 Rev. 0.3 February 1999
Absolute Maximum Ratings*
Core Supply Voltage to GND.............–0.5 to +4.6V
I/O Supply Voltage to GND................–0.5 to +4.6V
Input/Output to
GND Potential......... GNDQ–0.5 to V
Allowable Power Dissipation ..........................1.0W
Storage Temperature ...................... –65 to +150
Operating Temperature ......................... 0 to +70
CCQ
+0.5V
°
°
C
C
Note:
Exposure to conditions beyond those listed under
Absolute Maximum Ratings
and reliability of the device.
may adversely affect the life
Capacitance
V
CC
= 3.3 V, T
A
= 25
°
C, f = 1 MHz
* Note: These parameters are guaranteed by device
characterization and are not production tested.
Symbol
Parameter*
Conditions Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
I/O
Input/Output
Capacitance
V
OUT
= 0V
8
pF
Pin Names
Symbol
Type
Description
A0—A14
Input, Synchronous
Hot Address
I/O
0
-I/O
31
I/O, Synchronous
Data Inputs/Outputs
CLK
Input, Clock
Processor Host Bus Clock
CE1, CE2, CE3
Input, Synchronous
Chip Enables
GW
Input, Synchronous
Global Write
BWE
Input, Synchronous
Byte Write Enable from Cache Controller
BW
0
-BW
3
Input, Synchronous
Host BusByte Enables Used with BWE
OE
Input, Asynchronous
Output Enable Input
ADV
Input, Synchronous
Internal Burst Address Counter Advance
ADSC
Input, Synchronous
Address Status from CPU
ADSP
Input, Synchronous
Address Status from Chip Set
ZZ
Input, Asynchronous
Snooze Pin for Low-Power State
LBO
Input, Static
This Mode Selects Burst Sequence
LOW for Linear or HIGH for interleaved
V
CCQ
I/O Power Supply
GNDQ
I/O Ground
V
CC
Power Supply
GND
Ground
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