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參數(shù)資料
| 型號(hào)： | V63C31321024 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 32K X 32 CMOS Synchronous Burst Pipelined SRAM(32Kx32CMOS同步脈沖流水線式SRAM) |
| 中文描述： | 32K的× 32的CMOS SRAM的同步突發(fā)流水線（32Kx32CMOS同步脈沖流水線式的SRAM） |
| 文件頁(yè)數(shù)： | 1/16頁(yè) |
| 文件大?。?/td> | 119K |
| 代理商： | V63C31321024 |
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MOSEL V ITELIC
1
V63C31321024
32K X 32 CMOS
SYNCHRONOUS BURST
PIPELINED SRAM
PRELIMINARY
V63C31321024 Rev. 0.3 February 1999
Features
I
High-speed clock access time: 5/6/7/8ns
I
Single 3.3V power supply
I
Synchronous operation
I
Individual byte write control and global write
I
Internal registers for address, data, and controls
I
Output data registers
I
Asynchronous Output Enable
I
Supports snooze mode (low-power state)
I
Internal burst counter supports interleaved or lin-
ear burst mode
I
Available in 100-pin PQFP/TQFP
Functional Description
The V63C31321024 is a high-speed synchro-
nous burst pipelined CMOS SRAM organized as
32,768 words by 32 bits that supports both i486/
Pentium Interleaved mode and 680X0/Power
PC linear mode address pipelining. Control is
achieved through the use of the LBO pin.
Burst operations can be initiated with either the
address status processor (ADSP) or address status
cache controller (ADSC) inputs. Subsequently burst
addresses can be internally generated as controlled
by the burst advance (ADV) input.
The V63C31321024 operates on a single 3.3V
power supply and is ideally suited for applica-
tions that require high-speed, low-power and
wide-bit configuration in secondary cache designs.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
Q
U
5
6
7
8
Std.
0
°
C to 70
°
C
Blank
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