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參數(shù)資料
| 型號(hào)： | V63C31364097 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 128K X 36 CMOS Synchronous Burst Flow-Through SRAM(128Kx36CMOS同步脈沖流經(jīng)過的SRAM) |
| 中文描述： | 128K的米鼠36的CMOS同步突發(fā)流量通過的SRAM（128Kx36CMOS同步脈沖流經(jīng)過的靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 73K |
| 代理商： | V63C31364097 |
MOSEL V ITELIC
1
V63C31364097
128K X 36 CMOS
SYNCHRONOUS BURST
FLOW-THROUGH SRAM
PRELIMINARY
V63C31364097 Rev. 0.4 February 1999
Features
I
Single +3.3V (+10%/-5%) power supply
I
High Speed clock access time: 7.5ns/8ns/10ns
I
Flow through cycle time: 8.5ns/10ns/11ns
I
ADSP, ADSC, and ADV burst control pins
I
Individual byte write and global write control
I
Supports both Linear and Interleaved burst se-
quencing
I
Internal self-timed write cycle
I
Supports snooze mode (low power state)
I
User controlled I/O VDDQ pin
I
Available in 100 pin TQFP package
Functional Description
The V63C31364097 is a high speed 4M synchro-
nous burst CMOS Static RAM organized as 128K
words by 36 bits that supports high performances
secondary cache applications of the Pentium and
PowerPC microprocessors. The flow-through de-
sign allows output data to flow freely from the mem-
ory array during the read mode.
Burst operation can be initiated with either the
ADSP or ADSC inputs. Subsequent burst address-
es can be internally generated and controlled by the
bust advance (ADV) input.
Synchronous byte write (SBX), global write
(SGW) and write enable (SW) control allow writes
be made to either individual bytes or to all bytes.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
U
7.5
8
8.5
.,
Std.
0
°
C to 70
°
C
Blank
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