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參數(shù)資料
| 型號(hào)： | V63C31364097 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 128K X 36 CMOS Synchronous Burst Flow-Through SRAM(128Kx36CMOS同步脈沖流經(jīng)過(guò)的SRAM) |
| 中文描述： | 128K的米鼠36的CMOS同步突發(fā)流量通過(guò)的SRAM（128Kx36CMOS同步脈沖流經(jīng)過(guò)的靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 73K |
| 代理商： | V63C31364097 |
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V63C31364097 Rev. 0.4 February 1999
MOSEL V ITELIC
V63C31364097
Pin Descriptions
Pin Locations
Symbol
Type
Description
85
ADSC
Input
Synchronous Address Status Controller: Initiates READ, WRITE, or
chip deselect cycle
84
ADSP
Input
Synchronous Address Status Processor: Initiates READ, WRITE, or
chip deselect cycle (exception — chip deselect does not occur when
ADSP is asserted and SE1 is high.)
83
ADV
Input
Synchronous Address Advance: Increments address count in accor-
dance with counter type selected (linear/interleaved)
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63
(oo) 68, 69, 72, 73, 74, 75, 78, 79, 80
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
DQx
I/O
Synchronous Data l/O: "x" refers to the byte being read or written
(byte a, b, c, d)
86
G
Input
Asynchronous Output Enable Input:
Low—enables output buffers (DOx pins)
High—DOx pins are high impedance
89
K
Input
Clock: This signal registers the address, data in, and all control sig-
nals except G and LBO.
31
LBO
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low—linear burst counter(68K/PowerPC).
High—Interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46,
47, 48, 49, 50, 81, 82, 99, 100
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
36, 37
SA1,
SAo
Input
Synchronous Address Inputs. These pins must be wired to the two
LSBs ot the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
93, 94, 95, 96
(a) (b) (c) (d)
SBx
Input
Synchronous Byte Write Inputs "x" refers to the byte being written
(byte a, b, c, d) SGW overrides SBx.
98
SE 1
Input
Synchronous Chip Enable: Active low to enable chip.
Negated high — blocks ADSP or deselects chip when ADSC is
asserted.
97
SE2
Input
Synchronous Chip Enable: Active high for depth expansion.
92
SE3
Synchronous Chip Enable: Active low for depth expansion.
88
SGW
Input
Synchronous Global: This signal writes all bytes regardless of the
status of the SBx and SW signals. If only byte write signals SBx are
being used, tie this pin high.
87
SW
Input
Synchronous Write: This signal writes only those bytes that have
been selected using the byte write SBx pins. If only byte write signals
SBx are being used, tie this pin low.
15, 41, 65, 91
VDD
Supply
Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77
VDDQ
Supply
I/O Power Supply.
5, 10,17, 21, 26, 40,
55, 60, 67, 71, 76, 90
VSS
Supply
Ground.
14, 16, 38, 39, 42, 43, 66
NC
—
No Connection: There is no connection to the chip.
64
ZZ
Input
Snooze pin for low-power state. Active HIGH input to activate.
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