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參數(shù)資料
| 型號(hào)： | V63C31321024 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 32K X 32 CMOS Synchronous Burst Pipelined SRAM(32Kx32CMOS同步脈沖流水線式SRAM) |
| 中文描述： | 32K的× 32的CMOS SRAM的同步突發(fā)流水線（32Kx32CMOS同步脈沖流水線式的SRAM） |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 119K |
| 代理商： | V63C31321024 |
5
V63C31321024 Rev. 0.3 February 1999
MOSEL V ITELIC
V63C31321024
Truth Table
Notes:
1.
For a detailed definition of read/write, see the Write Table (next page).
2.
A “X” means “don’t care,” “1” means logic HIGH, and “0” means logic LOW.
3.
The OE pin enables the data output but is not synchronous with the clock. All signals of the SRAM are sampled
synchronous to the bus clock except for the OE pin.
4.
On a write cycle that follows a read cycle, OE must be inactive prior to the start of write cycle to allow write data to
setup the SRAM. OE must also disable the output buffer prior to the finish of a write cycle to ensure the SRAM
data hold timing are met.
Cycle
Address
Used
CE1
CE2
CE3
ADSP
ADSC
ADV
OE
Data
Write
(1)
Unselected
No
1
X
X
X
0
X
X
Hi-Z
X
Unselected
No
0
X
1
0
X
X
X
Hi-Z
X
Unselected
No
0
0
X
0
X
X
X
Hi-Z
X
Unselected
No
0
X
1
1
0
X
X
Hi-Z
X
Unselected
No
0
0
X
1
0
X
X
Hi-Z
X
Begin Read
External
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
0
D-OUT
Read
Continue Read
Next
1
X
X
X
1
0
1
Hi-Z
Read
Continue Read
Next
1
X
X
X
1
0
0
D-OUT
Read
Suspend Read
Current
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
X
X
X
1
1
1
0
D-Out
Read
Suspend Read
Current
1
X
X
X
1
1
1
Hi-Z
Read
Suspend Read
Current
1
X
X
X
1
1
0
D-OUT
Read
Begin Write
Current
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
1
X
X
X
1
1
X
Hi-Z
Write
Begin Write
External
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
1
X
X
X
1
0
X
Hi-Z
Write
Suspend Write
Current
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
1
X
X
X
1
1
X
Hi-Z
Write
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