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參數(shù)資料
| 型號： | V58C2256804SHUD6E |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | 32M X 8 DDR DRAM, PDSO66 |
| 封裝： | 0.400 INCH, PLASTIC, MS-024FC, TSOP2-66 |
| 文件頁數(shù)： | 33/60頁 |
| 文件大?。?/td> | 1125K |
| 代理商： | V58C2256804SHUD6E |
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39
ProMOS TECHNOLOGIES
V58C2256(804/404/164)SH
V58C2256(804/404/164)SH Rev. 1.1 July 2010
NOTES: (continued)
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will
effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long
as the signal does not ring back above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmit-ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value.
Thus, from VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise.
7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected
to be set equal to VREF and must track variations in the DC level of VREF.
8. VID is the magnitude of the difference between the input level on CK and the input level on CK.
9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the
DC level of the same.
10. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle
time at CL = 2 for -6 with the outputs open.
11. Enables on-chip refresh and address counters.
12. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate.
13. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, T A = 25°C,
VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that
they are matched in loading.
14. Command/Address input slew rate = 0.5V/ns. For -5 and -6 with slew rates 1V/ns and faster, tIS and tIH are re-
duced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS and tIH has an additional 50ps
per each 100mV/ns reduction in slew rate from the 500mV/ns. If the slew rate exceeds 4.5V/ns, functionality is
uncertain.
15. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input
reference level for signals other than CK/CK is VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes,
CKE 0.3 x VDDQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT.
18. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters
are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or be-
gins driving (LZ).
19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
20. This is not a device limit. The device will operate with a negative value, but system performance could be
degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS
going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous
WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS.
22. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value
for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that
meets the maximum absolute value for tRAS.
23. The refresh period 64ms. This equates to an average refresh rate of 7.8s.
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