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參數(shù)資料
| 型號： | V55C1256164MGLI-75H |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PDSO54 |
| 封裝： | 0.400 INCH, GREEN, PLASTIC, TSSOP2-54 |
| 文件頁數(shù)： | 46/48頁 |
| 文件大?。?/td> | 634K |
| 代理商： | V55C1256164MGLI-75H |
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V55C1256164MG Rev.1.0 September 2008
ProMOS TECHNOLOGIES
V55C1256164MG
Power On and Initialization
The default power on state of the mode register is
supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the “NOP” state. The power
on voltage must not exceed VCC+0.15V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200
s is required followed by a
precharge of both banks using the precharge
command. Once all banks have been precharged,
the Mode Register and Extended Mode Register
Set Command must be issued to initialize the Mode
Register. A minimum of two Auto Refresh cycles
(CBR) are also required.These may be done before
or after programming the Mode Register. Failure to
follow these steps may lead to unpredictable start-
up modes.
Programming the Mode Register
The Mode register designates the operation
mode at the read or write cycle. This register is di-
vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cy-
cle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Opera-
tion mode field to differentiate between normal op-
eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate com-
mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in pre-
charged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is re-
quired. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set op-
eration. Address input data at this timing defines pa-
rameters to be set as shown in the previous table.
Extended Mode Register
The extended Mode Register controls functions
beyond those controlled by the Mode Register.
These additional functions are unique to the mobile
SDRAM and includes the selection of drive strength
(DS). The device has four drive strength options:
Full, 1/2, 1/4 or 1/8. And a Partial-Array Self-Re-
fresh field (PASR). The PASR field is used to spec-
ify whether partial bank 1/2, 1/4, 1/8, 1/16 or all
banks of the SDRAM array are enabled. Disabled
banks will not be refreshed in Self-Refresh mode
and written data will be lost. When only bank 0 is se-
lected, it’s possible to partially select only half or
more quarter of bank 0. The default setting for DS is
full-strength, while PASR is full memory. Both DS
and PASR can be set during the initialization se-
quence and can be modified when the part is idle.
Addtionally, the device has internal temperature
sensor control self refresh cycle automatically ac-
cording to the two temperature range; Max. 40 deg
C, and Max. 85 deg C. This is the device internal
Temperature Compensated Self Refresh (TCSR).
Read and Write Operation
When RAS is low and both CAS and WE are high
at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the select-
ed bank is activated and all of sense amplifiers as-
sociated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, tRCD, from the
RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access
modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 133 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation,
i.e., one of 1, 2, 4, 8. Column addresses are seg-
mented by the burst length and serial data accesses
are done within this boundary. The first column ad-
dress to be accessed is supplied at the CAS timing
and the subsequent addresses are generated auto-
matically by the programmed burst length and its
sequence. For example, in a burst length of 8 with
interleave sequence, if the first address is ‘2’, then
the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and
5.
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