
1
V55C1256164MG
256Mbit MOBILE SDRAM
1.8 VOLT, TSOP II / FBGA PACKAGE
16M X 16
V55C1256164MG Rev. 1.0 September 2008
75910
System Frequency (fCK)
133 MHz
111 MHz
100MHz
Clock Cycle Time (tCK3)
7.5ns
9.0 ns
10 ns
Clock Access Time (tAC3) CAS Latency = 3
6.0 ns
7.0 ns
8.0ns
Features
■ 4 banks x 4Mbit x 16 organization
■ High speed data transfer rates up to 133 MHz
■ Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency:1, 2, 3
■ Programmable Wrap Sequence: Sequential or
Interleave
■ Programmable Burst Length:
1, 2, 4, 8, Full page for Sequential Type
1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode and Clock Suspend Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval:
8192 cycles/64 ms [ 0 to 70
°C (Commercial)] ;
8192 cycles/64ms[-40 to 85
°C (Industrial)];
8192 cycles/32ms [-40 to 105
°C (H)];
8192 cycles/32ms [-40 to 125
°C (Extended)]
■
■ Available in 54-ball FBGA (with 9x6 ball array
with 3 depopulated rows, 8x10 mm), and 54 pin
TSOP II
■ VDD=1.8V, VDDQ=1.8V
■ LVCMOS Interface
■ Drive Strength (DS) Option: Full, 1/2, 1/4 and 1/8
■ Auto Temperature Compensated Self Refresh
(Auto TCSR)
■ Partial Array Self Refresh (PASR) option: Full,
1/2, 1/4, 1/8 and 1/16
■ Deep Power Down (DPD) mode
■ Programmable Power Reduction Feature by par-
tial array activation during Self-Refresh
■ Operating Temperature Range
Commercial (0
°C to 70°C)
Industrial (-40
°C to +85°C)
H (-40
°C to +105°C)
Extended(-40
°C to +125°C)
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Temperature
Mark
K / I
75
9
10
0
°C to 70°C
-40
°C to 85°C
I
-40
°C to 105°C
H
-40
°C to 125°C
E
note: When temperature is higher than 100
°C, TCSR and self-refresh is not guaranteed.