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參數(shù)資料
| 型號： | USS820D-DB |
| 英文描述： | USS-820D USB Device Controller |
| 中文描述： | 號- 820D USB設備控制器 |
| 文件頁數(shù)： | 8/58頁 |
| 文件大?。?/td> | 868K |
| 代理商： | USS820D-DB |
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8
Agere Systems Inc.
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Pin Information
(continued)
Table 2. Pin Descriptions
* Active-low signals within this document are indicated by an N following the symbol names.
Pins marked as NC must have no external connections, except where noted.
44-Pin MQFP
(USS-820D)
1
2
48-Pin TQFP
(USS-820TD)
2
3
Symbol
*
Type
Name/Description
V
DDA
XTAL1
P
I
3.3 V Power Supply for Analog PLL.
Crystal/Clock Input.
If the internal oscillator is used, this is
the crystal input. If an external oscillator is used, this is the
clock input.
Crystal/Clock Output.
If the internal oscillator is used, this
is the crystal output. If an external oscillator is used, this
output should be left unconnected.
3.3 V Power Supply for USB Transceiver.
USB Differential Data Bus Minus.
USB Differential Data Bus Plus.
Device Ground for USB Transceiver.
Address Bus.
This is the address bus for the controller to
access the register set.
Device Ground.
For compatibility with USS-820 revision B,
this pin can be connected to a controller address bit, as
long as it is guaranteed to be equal to 0 during register
accesses and meets all address pin timing requirements.
Device Ground.
3
4
XTAL2
O
4
5
6
7
5
6
7
8
V
DDT
DMNS
DPLS
V
SST
A[4:0]
P
I/O
I/O
P
I
12, 11, 10, 9,
8
13
13, 12, 11,
10, 9
14
V
SSX
P
14, 20, 21,
22, 23, 24,
34, 40
15
15, 22, 23,
24, 25, 26,
37, 43
16
V
SS0
,
V
SS1
,
V
SS2,
V
SSX
P
DSA
O
Data Set Available.
Indicates one or more receive data
sets are valid, or one or more transmit data sets are empty
(available). For compatibility with USS-820 revision B, this
output is 3-stated if MCSR.BDFEAT = 0.
USB Reset Detected.
Indicates a USB reset event has
been detected on USB. This pin will remain asserted until
the SSR.RESET register bit is cleared by firmware. For
compatibility with USS-820 revision B, this output is 3-
stated if MCSR.BDFEAT = 0.
No Connect.
18
19
USBR
O
16
1, 17, 20, 21,
27
18, 47
48
NC
—
17, 44
19
V
DD0
, V
DD1
DPPU
P
O
3.3 V Power Supply.
DPLS Pull-Up.
Can be used to supply power to the DPLS
1.5 k
pull-up resistor to allow firmware to simulate a
device physical disconnect. This pin is directly controlled by
the DPEN register bit.
Remote Wake-Up (Active-Low).
Device is initiating a
remote wake-up from a suspend condition. This input is
ignored if SCR register bit RWUPE = 0.
Suspend (Active-Low).
USB suspend has been detected;
chip has entered suspend (low power) mode. This pin is
deasserted when a wake-up event is detected.
25
28
RWUPN
I
26
29
SUSPN
O
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