參數(shù)資料
型號： USS820D-DB
英文描述： USS-820D USB Device Controller
中文描述： 號- 820D USB設(shè)備控制器
文件頁數(shù)： 31/58頁
文件大小： 868K
代理商： USS820D-DB
Agere Systems Inc.
31
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 27. Receive FIFO Byte-Count High and Low Registers (RXCNTH, RXCNTL)—Address: RXCNTH =
07H, RXCNTL = 06H; Default: RXCNTH = 0000 0000B, RXCNTL = 0000 0000B
High and low registers are in a two-register ring buffer that is used to store the byte count for the data packets
received in the receive FIFO specified by EPINDEX. These registers are endpoint indexed.
Table 28. Receive FIFO Control Register (RXCON)—Address: 08H; Default: 0000 0100B
Controls the receive FIFO specified by EPINDEX. This register is endpoint indexed.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
BC9
Bit 8
BC8
—
—
R
Bit 7
BC7
Bit 6
BC6
Bit 5
BC5
Bit 4
BC4
Bit 3
BC3
Bit 2
BC2
Bit 1
BC1
Bit 0
BC0
R
Bit
15:10
9:0
Symbol
—
BC[9:0]
Function/Description
Reserved.
Write 0s to these bits. Reads always return 0s.
Receive Byte Count (Read Only).
10-bit, ring buffer byte. Stores receive byte count
(RXCNT).
Bit 7
RXCLR
Bit 6
FFSZ1
Bit 5
FFSZ0
Bit 4
RXFFRC
Bit 3
RXISO
Bit 2
ARM
Bit 1
ADVWM
Bit 0
REVWP
R/W
Bit
7
Symbol
RXCLR
Function/Description
Receive FIFO Clear.
Setting this bit flushes the receive FIFO, resets all the read/write
pointers and markers, resets the RXSETUP, STOVW, EDOVW, RXVOID, RXERR, and
RXACK bits of the RXSTAT register, sets the RXEMP bit in RXFLG register, and clears all
other bits in RXFLG register. Hardware clears this bit when the flush operation is
completed. Setting this bit does not affect the RXSEQ bit of RXSTAT. This bit should only
be set when the endpoint is disabled or there is a FIFO error present. Firmware should
never set this bit to clear a SETUP packet. The next SETUP packet will automatically clear
the receive FIFO.
FIFO Size.
These bits select the size of the receive FIFO.
FFSZ[1:0]
Nonisochronous Size
Isochronous Size
00
16
01
64
10
8*
11
32*
6:5
FFSZ[1:0]
64
256
512
1024
* Assumes MCSR.FEAT = 1. If MCSR.FEAT = 0, these FFSZ settings indicate 64 bytes.
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