參數(shù)資料
型號(hào)： USS820D-DB
英文描述： USS-820D USB Device Controller
中文描述： 號(hào)- 820D USB設(shè)備控制器
文件頁數(shù)： 20/58頁
文件大?。?/td> 868K
代理商： USS820D-DB
20
Agere Systems Inc.
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 16. Start of Frame Low Register (SOFL)—Address: 0EH; Default: 0000 0000B
This register contains the lower 8 bits of the 11-bit time stamp received from the host.
* S = shared bit. See Special Firmware Action for Shared Register Bits section.
Table 17. Endpoint Index Register (EPINDEX)—Address: 0AH; Default: 0000 0000B
This register identifies the endpoint pair. The register’s contents select the transmit and receive FIFO pair and
serve as an index to endpoint-specific special function registers (SFRs).
* The EPINDEX register identifies the endpoint pair and selects the associated transmit and receive FIFO pair. The value in this register plus
SFR addresses select the associated band of endpoint-indexed SFRs (TXDAT, TXCON, TXFLG, TXCNTH/L, RXDAT, RXCON, RXFLG,
RXCNTH/L, EPCON, TXSTAT, and RXSTAT).
Bit 7
TS7
Bit 6
TS6
Bit 5
TS5
Bit 4
TS4
Bit 3
TS3
Bit 2
TS2
Bit 1
TS1
Bit 0
TS0
R/W (S*)
Bit
7:0
Symbol
TS[7:0]
Function/Description
Time Stamp Received from Host
. This time stamp is valid only if the SOFACK bit in
the SOFH register is set. TS[7:0] are the lower 8 bits of the 11-bit frame number
issued with an SOF token. The time stamp remains at its previous value if an artificial
SOF is generated, and it is up to firmware to update it. These bits are set and cleared
by hardware.
Bit 7
Bit 6
Bit 5
—
—
Bit 4
Bit 3
Bit 2
EPINX2
Bit 1
EPINX1
R/W
Bit 0
EPINX0
Bit
7:3
2:0
Symbol
—
EPINX[2:0]
Endpoint Index.
Function/Description
Reserved.
Write 0s to these bits. Reads always return 0s.
EPINDEX
*
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
Function Endpoint
Function Endpoint 0
Function Endpoint 1
Function Endpoint 2
Function Endpoint 3
Function Endpoint 4
Function Endpoint 5
Function Endpoint 6
Function Endpoint 7
The EPINDEX register must not be changed during a sequence of RXDAT reads of a
particular data set. See the Receive FIFO section for more details.
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