參數(shù)資料
型號(hào)： USS820D-DB
英文描述： USS-820D USB Device Controller
中文描述： 號(hào)- 820D USB設(shè)備控制器
文件頁(yè)數(shù)： 22/58頁(yè)
文件大小： 868K
代理商： USS820D-DB
22
Agere Systems Inc.
Data Sheet, Rev. 4
June 2001
USB Device Controller
USS-820D
Register Interface
(continued)
Table 19. Endpoint Transmit Status Register (TXSTAT)—Address: 0CH; Default: 0000 0000B
This register contains the current endpoint status of the transmit FIFO specified by EPINDEX. This register is
endpoint indexed.
* For normal operation, this bit should not be modified by the user except as required by the implementation of USB standard commands, such
as SET_CONFIGURATION, SET_INTERFACE, and CLEAR_FEATURE [stall]. The SIE handles all sequence bit tracking required by normal
USB traffic, as documented in the USB specification, Section 8.6.
Only writable if TXNAKE = 1.
Bit 7
TXSEQ
R/W*
Bit 6
TXDSAM
R/W
Bit 5
TXNAKE
R/W
Bit 4
Bit 3
TXSOVW
W*
Bit 2
TXVOID
R/W
Bit 1
TXERR
Bit 0
TXACK
TXFLUSH
R
R
Bit
7
Symbol
TXSEQ
Function/Description
Transmitter Current Sequence Bit (Read, Conditional Write).
* This bit is trans-
mitted in the next PID and toggled on a valid ACK handshake. This bit is toggled by
hardware on a valid SETUP token. This bit can be written by firmware if the TXSOVW
bit is set when written together with the next TXSEQ value.
Transmit Data-Set-Available Mode.
If set, a NAK response to an IN token causes
the corresponding RXAV/TXAV bit in the DSAV register to set, and the DSA output pin
to assert (if enabled by MCSR.BDFEAT), rather than the standard condition (transmit
data set empty). This only occurs on NAKs caused by TXFIF = 00. This bit must not
be set for isochronous endpoints. When reset to 0 (along with MCSR.FEAT,
MCSR.BDFEAT, and TXSTAT.TXNAKE), the device will behave like revision B.
Transmit NAK Mode Enable.
If set, a NAK response to an IN token causes the
TXVOID bit and the corresponding bits in the SBI/SBI1 register to set, causing an
IRQN interrupt (if enabled). This only occurs on NAKs caused by TXFIF = 00. This bit
must not be set for isochronous endpoints. When set this bit also changes the
meaning and usage of the TXSTAT.TXVOID bit. When reset to 0 (along with
MCSR.FEAT, MCSR.BDFEAT, and TXSTAT.TXDSAM), the device will behave like
revision B.
TXFLUSH
Transmit FIFO Packet Flushed (Read Only).
Updated at each SOF. When set, this
bit indicates that hardware flushed a stale isochronous data packet from the transmit
FIFO at SOF.
6
TXDSAM
5
TXNAKE
4
Behavior when MCSR.FEAT = 0:
To guard against a missed IN token in isochronous mode, if, with TXFIF[1:0] = 11,
no IN token is received for the current endpoint, hardware automatically flushes
the oldest packet and decrements the TXFIF[1:0] value. This flush does not occur
if there is only one data set present (TXFIF = 01/10).
Behavior when MCSR.FEAT = 1:
A firmware data set write causes a TXFIF bit to set. For isochronous endpoints,
this data set does not become visible to the host until the next SOF. The data set is
intended to be read out during that frame. If that read does not occur (possibly due
to a lost IN packet), that data set is flushed at the next SOF, setting TXFLUSH. If
firmware writes two data sets during a single frame (TXFIF must have equalled 00
at the start of that frame), the first, older data set written is flushed at the subse-
quent SOF, setting TXFLUSH.
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