P3.6/AD6/PWM
參數(shù)資料
型號： USB-I2C/LIN-CONV-Z
廠商： Analog Devices Inc
文件頁數(shù)： 29/104頁
文件大小： 0K
描述： USB TO I2C/LIN CONV BOARD
標準包裝： 1
附件類型： 適配器板
適用于相關(guān)產(chǎn)品： ARM7TDMI?
ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 30 of 104
Pin No.
Mnemonic
Description
46
P3.6/AD6/PWMTRIP/PLAI[14]
General-Purpose Input and Output Port 3.6/External Memory Interface/PWM Safety Cutoff/
Programmable Logic Array Input Element 14.
47
P3.7/AD7/PWMSYNC/PLAI[15]
General-Purpose Input and Output Port 3.7/External Memory Interface/PWM Synchronization/
Programmable Logic Array Input Element 15.
48
P2.7/PWM1L/MS3
General-Purpose Input and Output Port 2.7/PWM Phase 1 Low-Side Output/External Memory
Select 3.
49
P2.1/WS/PWM0H/PLAO[6]
General-Purpose Input and Output Port 2.1/External Memory Write Strobe/PWM Phase 0 High-
Side Output/Programmable Logic Array Output Element 6.
50
P2.2/RS/PWM0L/PLAO[7]
General-Purpose Input and Output Port 2.2/External Memory Read Strobe/PWM Phase 0 Low-
Side Output/Programmable Logic Array Output Element 7.
51
P1.7/SPM7/PLAO[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic
Array Output Element 0.
52
P1.6/SPM6/PLAI[6]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic
Array Input Element 6.
53
IOGND
Ground for GPIO (see Table 78). Typically connected to DGND.
54
IOVDD
3.3 V Supply for GPIO (see Table 78) and Input of the On-Chip Voltage Regulator.
55
P4.0/AD8/PLAO[8]
General-Purpose Input and Output Port 4.0/External Memory Interface/Programmable Logic
Array Output Element 8.
56
P4.1/AD9/PLAO[9]
General-Purpose Input and Output Port 4.1/External Memory Interface/Programmable Logic
Array Output Element 9.
57
P1.5/SPM5/PLAI[5]/IRQ3
Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic
Array Input Element 5/External Interrupt Request 3, Active High.
58
P1.4/SPM4/PLAI[4]/IRQ2
Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic
Array Input Element 4/External Interrupt Request 2, Active High.
59
P1.3/SPM3/PLAI[3]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable
Logic Array Input Element 3.
60
P1.2/SPM2/PLAI[2]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable
Logic Array Input Element 2.
61
P1.1/SPM1/PLAI[1]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable
Logic Array Input Element 1.
62
P1.0/T1/SPM0/PLAI[0]
Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/
Programmable Logic Array Input Element 0.
63
P4.2/AD10/PLAO[10]
General-Purpose Input and Output Port 4.2/External Memory Interface/Programmable Logic
Array Output Element 10.
64
P4.3/AD11/PLAO[11]
General-Purpose Input and Output Port 4.3/External Memory Interface/Programmable Logic
Array Output Element 11.
65
P4.4/AD12/PLAO[12]
General-Purpose Input and Output Port 4.4/External Memory Interface/Programmable Logic
Array Output Element 12.
66
P4.5/AD13/PLAO[13]
General-Purpose Input and Output Port 4.5/External Memory Interface/Programmable Logic
Array Output Element 13.
67
REFGND
Ground for the Reference. Typically connected to AGND.
68
VREF
2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the
internal reference.
69
DACREF
External Voltage Reference for the DACs. Range: DACGND to DACVDD.
70
DACGND
Ground for the DAC. Typically connected to AGND.
71, 72
AGND
Analog Ground. Ground reference point for the analog circuitry.
73, 74
AVDD
3.3 V Analog Power.
75
DACVDD
3.3 V Power Supply for the DACs. Must be connected to AVDD.
76
ADC11
Single-Ended or Differential Analog Input 11.
77
ADC0
Single-Ended or Differential Analog Input 0.
78
ADC1
Single-Ended or Differential Analog Input 1.
79
ADC2/CMP0
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
80
ADC3/CMP1
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
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