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參數(shù)資料
| 型號： | UR5596 |
| 廠商： | 友順科技股份有限公司 |
| 英文描述： | MOS IC |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 207K |
| 代理商： | UR5596 |
UR5596
MOS IC
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
QW-R502-045,A
8
FOR DDR-II APPLICATIONS
As a result of the separate V
DDQ
pin and an internal resistor divider,
UR5596
can be utilized in DDR-II system,
figure 5 and 6 show two recommended circuits in DDR-II SDRAM application. The output stage is connected to the
1.8V rail and the AV
IN
pin can be connected to either a 3.3V or 5V rail. If it is not desirable to use the 1.8V rail it is
possible to connect the output stage to a 3.3V rail. The power dissipation increasing concern must be careful as well
SSTL-II application. The advantage of configuration of figure 6 is that it has the ability to source and sink a higher
maximum continuous current.
+
+
+
V
TT
V
DDQ
V
SENSE
V
REF
GND
SHDN
AV
IN
PV
IN
C
IN
SHDN
V
DDQ
=1.8V
AV
IN
=2.2V
～
5.5V
C
OUT
C
REF
V
REF
=0.9V
V
TT
=0.9V
UTC UR5596
PV
IN
=1.8V
Figure 5. Recommended DDR-II Termination
+
+
+
V
TT
V
DDQ
V
SENSE
V
REF
GND
SHDN
AV
IN
PV
IN
C
IN
SHDN
V
DDQ
=1.8V
AV
IN
=3.3V or 5.5V
C
OUT
C
REF
V
REF
=0.9V
V
TT
=0.9V
UTC UR5596
PV
IN
=3.3V
Figure 6. DDR-II Termination with higher voltage rails
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| UR5596L-S08-R | MOS IC |
| UR5596L-S08-T | MOS IC |
| UR5596-S08-R | MOS IC |
| UR5596-S08-T | MOS IC |
| UR6225-xx-AB3-C-R | 5.0 AMP POSITIVE VOLTAGE REGULATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UR5596_07 | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596_10 | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596L-S08-R | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596L-S08-T | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596L-SH2-R | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
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