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參數(shù)資料
| 型號(hào)： | UR5596 |
| 廠商： | 友順科技股份有限公司 |
| 英文描述： | MOS IC |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 207K |
| 代理商： | UR5596 |
UR5596
MOS IC
UNISONIC TECHNOLOGIES CO., LTD
www.unisonic.com.tw
QW-R502-045,A
6
T Y PICAL APPLICAT ION CIRCUIT S
Following demonstrate several different application circuits to illustrate some of the options that are possible in
configuring the UTC
UR5596
. The individual circuit performance can be found in the Typical Performance
Characteristics that curve graphs illustrate how the maximum output current is affected by changes in AV
IN
and PV
IN
.
STUB-SERIES TERMINATED LOGIC(SSTL) TERMINATION SCHEME
SSTL was created to improve signal integrity of the data transmission across the memory bus. This termination
scheme is essential to prevent data error from signal reflections while transmitting at high frequencies encountered
with DDR-SDRAM. Class II single parallel termination(SSTL-2) is the most popular termination form. It involves one
R
S
series resistor from the chipset to the memory and one R
T
termination resistor (refer to Figure 1). R
S
and R
T
are
changeable to meet the current requirement from UR5596, the recommended values both R
S
and R
T
are 25
Ω
.
CHIPSET
R
S
R
T
MEMORY
V
REF
V
TT
V
DD
Figure 1. SSTL-Termination Scheme
FOR SSTL-2 APPLICATIONS
For the majority of applications that implement the SSTL- 2 termination scheme, it is recommended to connect all
the input rails to the 2.5V rail as Figure 2. This provides an optimal trade-off between power dissipation and
component count and selection.
+
+
+
V
TT
V
DDQ
V
SENSE
V
REF
GND
SHDN
AV
IN
PV
IN
C
IN
SHDN
V
DDQ
=2.5V
V
DD
=2.5V
C
OUT
C
REF
V
REF
=1.25V
V
TT
=1.25V
UTC UR5596
Figure 2. Recommended SSTL-2 Implementation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UR5596L-S08-R | MOS IC |
| UR5596L-S08-T | MOS IC |
| UR5596-S08-R | MOS IC |
| UR5596-S08-T | MOS IC |
| UR6225-xx-AB3-C-R | 5.0 AMP POSITIVE VOLTAGE REGULATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UR5596_07 | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596_10 | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596L-S08-R | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596L-S08-T | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596L-SH2-R | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
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