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參數(shù)資料
| 型號： | UR5596 |
| 廠商： | 友順科技股份有限公司 |
| 英文描述： | MOS IC |
| 中文描述： | 馬鞍山集成電路 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 207K |
| 代理商： | UR5596 |
UNISONIC TECHNOLOGIES CO,LTD
UR5596
MOS IC
www.unisonic.com.tw
Copyright 2005 Unisonic Technologies Co.,LTD
1
QW-R502-045,A
DDR T ERMINAT ION
REGULAT OR
DES CRIPT ION
The UTC
UR5596
is a linear bus termination regulator and
designed to meet JEDEC SSTL-2(Stub-Series Terminated
Logic) specifications for termination of DDR-SDRAM. It also can
be used in SSTL-3 or HSTL(High-Speed Transceiver Logic)
scheme. The device contains a high-speed OP AMP to provide
excellent response to the load transients, and can deliver 1.5A
continuous current and transient peaks up to 3A in the
application as required for DDR-SDRAM termination.
The UTC
UR5596
also incorporates a V
SENSE
pin to provide
superior load regulation and a V
REF
output as a reference for the
chipset and DIMMs. Besides, an active low shutdown (SHDN)
pin provides Suspend To RAM (STR) functionality. When SHDN
is pulled low the V
TT
output will tri-state providing a high
impedance output, but, V
REF
will remain active. A power savings
advantage can be obtained in this mode through lower
quiescent current.
Regarding the output, V
TT
is capable of sinking and sourcing
current while regulating the output voltage equal to V
DDQ
/2. The
output stage has been designed to maintain excellent load
regulation while preventing shoot through. The UTC
UR5596
also incorporates two distinct power rails that separates the
analog circuitry from the power output stage. This allows a split
rail approach to be utilized to decrease internal power
dissipation and permits UTC
UR5596
to provide a termination
solution for DDRII SDRAM.
FEAT URES
* Source and sink current
* Low output voltage offset
* No external resistors required
* Linear topology
* Suspend To Ram (STR) functionality
* Low external component count
* Thermal shutdown protection
SOP-8
*Pb-free plating product number: UR5596L
ORDERING INFORMAT ION
Ordering Number
Normal
UR5596-S08-R
UR5596-S08-T
Lead Free Plating
UR5596L-S08-R
UR5596L-S08-T
Package
Packing
SOP-8
SOP-8
Tape Reel
Tube
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UR5596L-S08-R | MOS IC |
| UR5596L-S08-T | MOS IC |
| UR5596-S08-R | MOS IC |
| UR5596-S08-T | MOS IC |
| UR6225-xx-AB3-C-R | 5.0 AMP POSITIVE VOLTAGE REGULATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UR5596_07 | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596_10 | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596L-S08-R | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596L-S08-T | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
| UR5596L-SH2-R | 制造商:UTC-IC 制造商全稱:UTC-IC 功能描述:DDR TERMINATION REGULATOR |
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