
uPSD33xx
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8032 ADDRESSING MODES
The 8032 MCU uses 11 different addressing
modes listed below:
Register
Direct
Register Indirect
Immediate
External Direct
External Indirect
Indexed
Relative
Absolute
Long
Bit
Register Addressing
This mode uses the contents of one of the regis-
ters R0 - R7 (selected by the last three bits in the
instruction opcode) as the operand source or des-
tination. This mode is very efficient since an addi-
tional instruction byte is not needed to identify the
operand. For example:
■
■
■
■
■
■
■
■
■
■
■
Direct Addressing
This mode uses an 8-bit address, which is con-
tained in the second byte of the instruction, to di-
rectly address an operand which resides in either
8032 DATA SRAM (internal address range 00h-
07Fh) or resides in 8032 SFR (internal address
range 80h-FFh). This mode is quite fast since the
range limit is 256 bytes of internal 8032 SRAM.
For example:
Register Indirect Addressing
This mode uses an 8-bit address contained in ei-
ther Register R0 or R1 to indirectly address an op-
erand which resides in 8032 IDATA SRAM
(internal address range 80h-FFh). Although 8032
SFR registers also occupy the same physical ad-
dress range as IDATA, SFRs will not be accessed
by Register Indirect mode. SFRs may only be ac-
cesses using Direct address mode. For example:
Immediate Addressing
This mode uses 8-bits of data (a constant) con-
tained in the second byte of the instruction, and
stores it into the memory location or register indi-
cated by the first byte of the instruction. Thus, the
data is immediately available within the instruction.
This mode is commonly used to initialize registers
and SFRs or to perform mask operations.
There is also a 16-bit version of this mode for load-
ing the DPTR Register. In this case, the two bytes
following the instruction byte contain the 16-bit val-
ue. For example:
External Direct Addressing
This mode will access external memory (XDATA)
by using the 16-bit address stored in the DPTR
Register. There are only two instructions using this
mode and both use the accumulator to either re-
ceive a byte from external memory addressed by
DPTR or to send a byte from the accumulator to
the address in DPTR. The uPSD33xx has a spe-
cial feature to alternate the contents (source and
destination) of DPTR rapidly to implement very ef-
ficient memory-to-memory transfers. For example:
Note:
POINTERS, page 37
.
See
details
in
DUAL
DATA
External Indirect Addressing
This mode will access external memory (XDATA)
by using the 8-bit address stored in either Register
R0 or R1. This is the fastest way to access XDATA
(least bus cycles), but because only 8-bits are
available for address, this mode limits XDATA to a
size of only 256 bytes (the traditional Port 2 of the
8032 MCU is not available in the uPSD33xx, so it
is not possible to write the upper address byte).
This mode is not supported by uPSD33xx.
For example:
MOV A, R7
; Move contents of R7 to accumulator
MOV A, 40h
; Move contents of DATA SRAM
; at location 40h into the accumulator
MOV A, @R0
; Move into the accumulator the
; contents of IDATA SRAM that is
; pointed to by the address
; contained in R0.
MOV A, 40#
; Move the constant, 40h, into
; the accumulator
MOV DPTR, 1234# ; Move the constant, 1234h, into
; DPTR
MOVX A, @DPTR ; Move contents of accumulator to
; XDATA at address contained in
; DPTR
MOVX @DPTR, A ; Move XDATA to accumulator
MOVX @R0,A
; Move into the accumulator the
; XDATA that is pointed to by
; the address contained in R0.