參數(shù)資料
型號: UPSD3233BV-40U1T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和64Kbit SRAM的
文件頁數(shù): 53/176頁
文件大?。?/td> 1081K
代理商: UPSD3233BV-40U1T
53/176
μ
PSD323X
TIMER/COUNTERS (TIMER0, TIMER1 AND TIMER2)
The
μ
PSD323X Devices has three 16-bit Timer/
Counter registers: Timer 0, Timer 1 and Timer2.
All of them can be configured to operate either as
timers or event counters and are compatible with
standard 8032 architecture.
In the “Timer” function, the registeris incremented
every machine cycle. Thus, one can think of it as
counting machine cycles. Since a machine cycle
consists of 6 CPU clock periods, the count rate is
1/6 of the CPU clock frequency.
In the “Counter”function, theregister is increment-
ed in response to a 1-to-0 transition at its corre-
sponding external input pin, T0 or T1. In this
function, the external input is sampled during
S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in thenext cy-
cle, thecount is incremented. The new count value
appears in the register during S2P1 of the cycle
following the one in which the transition was de-
tected. Since it takes 2 machine cycles (12 CPU
clock periods) to recognize a 1-to-0 transition, the
maximum count rate is 1/12 of the CPU clock fre-
quency. There are norestrictions onthe duty cycle
of the external input signal, but to ensure that a
given level is sampled at least once before it
changes, it should be held for at least one full cy-
cle. In addition to the “Timer” or “Counter” selec-
tion, Timer0 and Timer1 have four operating
modes from which to select.
Timer0 and Timer1
The “Timer” or “Counter” function is selected by
control bits C/ T in the Special Function Register
TMOD. These Timer/Counters have four operat-
ing modes, which are selected by bit-pairs (M1,
M0) in TMOD.Modes 0, 1, and 2 are the same for
Timers/ Counters. Mode 3 is different. The four op-
erating modes are de-scribed in the following text.
Table 36. Control Register (TCON)
Table 37. Description of the TCON Bits
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
Symbol
Function
7
TF1
Timer 1overflow flag. Set by hardware onTimer/Counter overflow. Cleared by hardware
when processor vectors to interrupt routine
6
TR1
Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on or off
5
TF0
Timer 0 overflow flag. Set by hardier on Timer/Counter overflow. Cleared by hardware
when processor vectors to interrupt routine
4
TR0
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on or off
3
IE1
Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed
2
IT1
Interrupt 1 Typecontrol bit. Set/cleared by software to specify falling-edge/low-level
triggered external interrupt
1
IE0
Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed
0
IT0
Interrupt 0 Typecontrol bit. Set/cleared by software to specify falling-edge/low-level
triggered external interrupt
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