- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361591 > UPSD3233BV-40U1T (意法半導(dǎo)體) Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM PDF資料下載
參數(shù)資料
| 型號： | UPSD3233BV-40U1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM |
| 中文描述： | 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和64Kbit SRAM的 |
| 文件頁數(shù)： | 39/176頁 |
| 文件大?。?/td> | 1081K |
| 代理商： | UPSD3233BV-40U1T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁
39/176
μ
PSD323X
INTERRUPT SYSTEM
There are interrupt requests from 10 sources as
follows.
I
INT0 external interrupt
I
2nd USART interrupt
I
Timer0 interrupt
I
I
2
C interrupt
I
INT1 external interrupt (or ADC interrupt)
I
DDC interrupt
I
Timer1 interrupt
I
USB interrupt
I
USART interrupt
I
Timer2 interrupt
External Int0
I
The INT0canbe eitherlevel-active ortransition-
active depending on Bit IT0 in register TCON.
The flag that actually generates this interrupt is
Bit IE0 in TCON.
I
When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
I
If the interrupt was level activated then the
interrupt request flag remains set until the
requested interrupt is actually generated. Then
it has to deactivate the request before the
interrupt service routine is completed, or else
another interrupt will be generated.
Timer 0 and 1 Interrupts
I
Timer0 and Timer1 interrupts are generated by
TF0 and TF1 which are set by an overflow of
theirrespectiveTimer/Counterregisters(except
for Timer0 in Mode 3).
I
These flags are cleared by the internal
hardware when the interrupt is serviced.
Timer 2 Interrupt
I
Timer2 interrupt is generated by TF2 which is
set byan overflow of Timer2.This flaghas to be
cleared by the software - not by hardware.
I
It is also generated by the T2EX signal (timer 2
external interrupt P1.1) which is controlled by
EXEN2 and EXF2 Bits in the T2CON register.
This is the definition of Timer 2 as per 90C320
definition.
I
2
C Interrupt
I
The interrupt ofthe I
2
C is generatedby Bit INTR
in the register S2STA.
I
This flag is cleared by hardware.
External Int1
I
The INT1 canbe either level active ortransition
active depending on Bit IT1 in register TCON.
The flag that actually generates this interrupt is
Bit IE1 in TCON.
I
When an external interrupt is generated, the
corresponding request flag is cleared by the
hardware when the service routine is vectored
to only if the interrupt was transition activated.
I
If the interrupt was level activated then the
interrupt request flag remains set until the
requested interrupt is actually generated. Then
it has to deactivate the request before the
interrupt service routine is completed, or else
another interrupt will be generated.
I
The ADC can take over the External INT1 to
generate an interrupt on conversion being
completed
DDC Interrupt
I
The DDC interrupt is generated either by Bit
INTR in the S1STA register for DC2B protocol
or by Bit DDC interrupt in the DDCCON register
for DDC1 protocol or by Bit SWHINT Bit in the
DDCCON register when DDC protocol is
changed from DDC1 to DDC2.
I
Flags excepttheINTRhave to becleared by the
software. INTR flag is cleared by hardware.
USB Interrupt
I
The USB interruptis generatedwhen endpoint0
has transmitted a packet or received a packet,
when endpoint1 orendpoint2 has transmitted a
packet, when the suspend or resume state is
detected and every EOP received.
I
When the USB interrupt is generated, the
corresponding request flag must be cleared by
software. The interrupt serviceroutine will have
to checkthe various USB registers todetermine
the source and clear the corresponding flag.
I
Please see thededicated interrupt control
registers for the USB peripheral for more
information.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| uPSD3233 | Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器) |
| uPSD3234(中文) | Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器) |
| uPSD3212C(中文) | Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件) |
| uPSD3254A(中文) | Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件) |
| uPSD3254BV(中文) | Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPSD3233BV-40U6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
| UPSD3233BV-40U6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD32348V24V6ES | 制造商:ST MICRO 功能描述:* |
| UPSD3234A | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core |
| UPSD3234A-24T1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。