參數(shù)資料
型號(hào): UPSD3233BV-40U1T
廠商: 意法半導(dǎo)體
英文描述: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
中文描述: 閃存可編程系統(tǒng)設(shè)備與8032微控制器核心和64Kbit SRAM的
文件頁(yè)數(shù): 21/176頁(yè)
文件大?。?/td> 1081K
代理商: UPSD3233BV-40U1T
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)
21/176
μ
PSD323X
(3) Register addressing.
The
containing registers R0 through R7, can be ac-
cessed by certain instructions which carry a 3-bit
register specification within the opcode of the in-
struction. Instructions that access the registers
this way are code efficient, since this mode elimi-
nates anaddress byte. When the instruction is ex-
ecuted, one of four banks is selected at execution
time by the two bank select bits in the PSW.
Example:
mov PSW, #0001000B ; select Bank0
mov A, #30H
mov R1, A
(4) Register-specific addressing.
Some
structions are specific to a certain register. For ex-
ample, some instructions always operate on the
Accumulator, or Data Pointer, etc., so no address
byte is needed to point it. The opcode itself does
that.
(5) Immediate constants addressing.
The val-
ue of a constantcan follow theopcode in Program
memory.
Example:
mov A, #10H.
(6) Indexed addressing.
Only Program memory
can be accessed with indexed addressing, and it
can only be read. Thisaddressing modeis intend-
ed for reading look-up tables in Program memory.
A 16-bit base register (either DPTR or PC) points
to the base of the table,and theAccumulator is set
up with the table entry number. The address of the
table entry in Program memory is formed by add-
ing the Accumulator data to the base pointer.
Example:
movc A, @A+DPTR
register
banks,
in-
Figure 13. Indexed Addressing
Arithmetic Instructions
The arithmetic instructions is listed in Table 4,
page 22. The table indicates the addressing
modes that can be used with each instruction to
access the <byte> operand. For example, the
ADD A, <byte> instruction can be written as:
ADD a, 7FH(direct addressing)
ADD A, @R0 (indirect addressing)
ADD a, R7 (register addressing)
ADD A, #127 (immediate constant)
Note:
Any byte in the internal DataMemory space
can be incremented without going through theAc-
cumulator.
One of theINC instructions operates on the 16-bit
Data Pointer.The Data Pointer is used to generate
16-bit addresses for external memory, so being
able to increment it in one 16-bit operations is
a useful feature.
The MUL AB instruction multiplies the Accumula-
tor by the data in the B registerand puts the16-bit
product into the concatenated B and Accumulator
registers.
The DIV AB instruction divides the Accumulator by
the data in the B register and leaves the 8-bit quo-
tient inthe Accumulator, and the 8-bit remainder in
the B register.
In shift operations, dividing a number by 2n shifts
its “n” bits to theright. Using DIV AB to performthe
division completes the shift in 4s and leaves the
B register holding the bits that were shifted out.
The DAA instruction is for BCD arithmetic opera-
tions. In BCD arithmetic, ADD and ADDC instruc-
tions should always be followed by a DAA
operation, to ensure that the result is also in BCD.
Note:
DAA will not convert a binary number to
BCD. The DAA operation produces a meaningful
result only as the second step in the addition of
two BCD bytes.
AI06643
3Eh
Program Memory
ACC
3Ah
DPTR
1E73h
相關(guān)PDF資料
PDF描述
uPSD3233 Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3234(中文) Flash Programmable System Device with 8032 Microcontroller Core(嵌入高速“8032微控制器核”的Flash型可編程系統(tǒng)器)
uPSD3212C(中文) Flash Programmable System Devices with 8032 Microcontroller Core and 16Kbit SRAM(帶8032微控制器內(nèi)核和16Kbit SRAM的FLASH可編程系統(tǒng)器件)
uPSD3254A(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
uPSD3254BV(中文) Flash Programmable System Devices with 8032 Microcontroller Core(帶8032微控制器內(nèi)核的FLASH可編程系統(tǒng)器件)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPSD3233BV-40U6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core
UPSD3233BV-40U6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD32348V24V6ES 制造商:ST MICRO 功能描述:*
UPSD3234A 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Devices with 8032 Microcontroller Core
UPSD3234A-24T1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash Programmable System Device with 8032 Microcontroller Core