參數(shù)資料
型號(hào): UPD78F9510GR-JJG-A
廠商: Renesas Electronics America
文件頁數(shù): 59/175頁
文件大小: 0K
描述: MCU 8BIT SGL CHIP 16PIN
標(biāo)準(zhǔn)包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 1KB(1K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SSOP(0.173",4.40mm 寬)
包裝: 托盤
CHAPTER 8 WATCHDOG TIMER
User’s Manual U16994EJ6V0UD
149
8.3
Registers Controlling Watchdog Timer
The watchdog timer is controlled by the following two registers.
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
(1) Watchdog timer mode register (WDTM)
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
Reset signal generation sets this register to 67H.
Figure 8-2. Format of Watchdog Timer Mode Register (WDTM)
0
WDCS0
1
WDCS1
2
WDCS2
3
WDCS3
4
WDCS4
5
1
6
1
7
0
Symbol
WDTM
Address: FF48H
After reset: 67H
R/W
WDCS4
Note 1
WDCS3
Note 1
Operation clock selection
0
Low-speed internal oscillation clock (fRL)
0
1
System Clock (fX)
1
×
Watchdog timer operation stopped
Overflow time setting
WDCS2
Note 2
WDCS1
Note 2
WDCS0
Note 2
During low-speed internal
oscillation clock operation
During system clock operation
0
2
11/fRL (4.27 ms)
2
13/fX (819.2
μs)
0
1
2
12/fRL (8.53 ms)
2
14/fX (1.64 ms)
0
1
0
2
13/fRL (17.07 ms)
2
15/fX (3.28 ms)
0
1
2
14/fRL (34.13 ms)
2
16/fX (6.55 ms)
1
0
2
15/fRL (68.27 ms)
2
17/fX (13.11 ms)
1
0
1
2
16/fRL (136.53 ms)
2
18/fX (26.21 ms)
1
0
2
17/fRL (273.07 ms)
2
19/fX (52.43 ms)
1
2
18/fRL (546.13 ms)
2
20/fX (104.86 ms)
Notes 1.
If “l(fā)ow-speed internal oscillator cannot be stopped” is specified by the option byte, this cannot
be set.
The low-speed internal oscillation clock will be selected no matter what value is
written.
2.
Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Caution
1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively
. Do not set the other values.
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