參數(shù)資料
型號: UPD78F9510GR-JJG-A
廠商: Renesas Electronics America
文件頁數(shù): 161/175頁
文件大?。?/td> 0K
描述: MCU 8BIT SGL CHIP 16PIN
標(biāo)準(zhǔn)包裝: 400
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 1KB(1K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SSOP(0.173",4.40mm 寬)
包裝: 托盤
CHAPTER 5 CLOCK GENERATORS
User’s Manual U16994EJ6V0UD
84
(2) Crystal/ceramic oscillator
If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 MHz to 10 MHz can be selected
and the accuracy of processing is improved because the frequency deviation is small, as compared with high-
speed internal oscillation (8 MHz (TYP.)).
Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic
oscillator.
Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator
VDD
Crystal/ceramic
oscillator clock
PCC = 02H, PPCC = 02H
(a)
(b)
(c)
H
RESET
System clock
Internal reset
CPU clock
Option byte is read.
System clock is selected.
(Operation stops
Note 1)
Clock oscillation
stabilization
timeNote 2
Notes 1. Operation stop time is 276
μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).
2. The clock oscillation stabilization time for default start is selected by the option byte. For details, refer to
CHAPTER 15 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode is
released is selected by the oscillation stabilization time select register (OSTS).
(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is
referenced after reset, and the system clock is selected.
(b) After high-speed internal oscillation clock is generated, the option byte is referenced and the system clock is
selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock.
(c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock
oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 15
OPTION BYTE.
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