μPD78F921x ONLY) User’s Manual U16994EJ6V0UD 158 Table 9-1. Sampling Time and" />
參數(shù)資料
型號： UPD78F9210GR-JJG-A
廠商： Renesas Electronics America
文件頁數(shù)： 69/175頁
文件大?。?/td> 0K
描述： MCU 8BIT 1KB FLASH MEM 16-SSOP
標準包裝： 1
系列： 78K0S/Kx1+
核心處理器： 78K0S
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 13
程序存儲器容量： 1KB（1K x 8）
程序存儲器類型： 閃存
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 16-SSOP（0.173"，4.40mm 寬）
包裝： 托盤
其它名稱： 972-1045
UPD78F9210GR-JJG-A-ND
CHAPTER 9 A/D CONVERTER (
μPD78F921x ONLY)
User’s Manual U16994EJ6V0UD
158
Table 9-1. Sampling Time and A/D Conversion Time
fXP = 8 MHz
fXP = 10 MHz
Reference
Voltage
Range
Note 1
Sampling
Time
Note 2
Conversion
Time
Note 3
Sampling
Time
Note 2
Conversion
Time
Note 3
Sampling
Time
Note 2
Conversion
Time
Note 3
FR2
FR1
FR0
VDD
≥ 4.5 V
12/fXP
36/fXP
1.5
μs
4.5
μs
1.2
μs
3.6
μs
0
VDD
≥ 4.0 V
24/fXP
72/fXP
3.0
μs
9.0
μs
2.4
μs
7.2
μs
1
0
96/fXP
144/fXP
12.0
μs
18.0
μs
9.6
μs
14.4
μs
1
0
48/fXP
96/fXP
6.0
μs
12.0
μs
4.8
μs
9.6
μs
1
0
1
48/fXP
72/fXP
6.0
μs
9.0
μs
4.8
μs
7.2
μs
0
1
0
VDD
≥ 2.85 V
24/fXP
48/fXP
3.0
μs
6.0
μs
Setting
prohibited
Note 4
(2.4
μs)
Setting
prohibited
Note 4
(4.8
μs)
0
1
176/fXP
224/fXP
22.0
μs
28.0
μs
17.6
μs
22.4
μs
1
VDD
≥ 2.7 V
88/fXP
112/fXP
11.0
μs
14.0
μs
Setting
prohibited
Note 4
(8.8
μs)
Setting
prohibited
Note 4
(11.2
μs)
0
1
Notes 1.
Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 2 and 3
below are satisfied.
Example When VDD
≥ 2.7 V, fXP = 8 MHz
The sampling time is 11.0
μs or more and the A/D conversion time is 14.0 μs or more and 100 μs or
less.
Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1.
2.
Set the sampling time as follows.
VDD ≥ 4.5 V:
1.0
μs or more
VDD ≥ 4.0 V:
2.4
μs or more
VDD ≥ 2.85 V:
3.0
μs or more
VDD ≥ 2.7 V:
11.0
μs or more
3.
Set the A/D conversion time as follows.
VDD ≥ 4.5 V:
3.0
μs or more and less than 100 μs
VDD ≥ 4.0 V:
4.8
μs or more and less than 100 μs
VDD ≥ 2.85 V:
6.0
μs or more and less than 100 μs
VDD ≥ 2.7 V:
14.0
μs or more and less than 100 μs
4.
Setting is prohibited because the values do not satisfy the condition of Notes 2 or 3.
Caution
The above sampling time and conversion time do not include the clock frequency error. Select
the sampling time and conversion time such that Notes 2 and 3 above are satisfied, while taking
the clock frequency error into consideration (an error margin maximum of
±5% when using the
high-speed internal oscillator).
Remarks 1.
fXP: Oscillation frequency of clock to peripheral hardware
2.
The conversion time refers to the total of the sampling time and the time from successively
comparing with the sampling value until the conversion result is output.
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