參數(shù)資料
型號(hào): UPD78F9210GR-JJG-A
廠商: Renesas Electronics America
文件頁數(shù): 120/175頁
文件大小: 0K
描述: MCU 8BIT 1KB FLASH MEM 16-SSOP
標(biāo)準(zhǔn)包裝: 1
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 1KB(1K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SSOP(0.173",4.40mm 寬)
包裝: 托盤
其它名稱: 972-1045
UPD78F9210GR-JJG-A-ND
CHAPTER 3 CPU ARCHITECTURE
User’s Manual U16994EJ6V0UD
47
3.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents.
The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed.
When a branch instruction is executed, the branch destination address
information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S
Series Instructions User’s Manual (U11047E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start
address of the following instruction is transferred to the program counter (PC) to branch. The displacement
value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes the sign bit. In other words,
the range of branch in relative addressing is between –128 and +127 of the start address of the following
instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
0
PC
15
0
S
15
0
PC
+
87
6
α
jdisp8
When S = 0,
α indicates that all bits are “0”.
... PC is the start address of
the next instruction of
a BR instruction.
When S = 1,
α indicates that all bits are “1”.
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