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參數(shù)資料
| 型號(hào)： | UPD75238GJ |
| 廠商： | NEC Corp. |
| 英文描述： | 4 BIT SINGLE-CHIP MICROCOMPUTER |
| 中文描述： | 4位單片機(jī) |
| 文件頁(yè)數(shù)： | 22/190頁(yè) |
| 文件大?。?/td> | 1702K |
| 代理商： | UPD75238GJ |
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22
μ
PD75238
2.3 MEMORY-MAPPED I/O
The
μ
PD75238 employs memory-mapped I/O, which maps peripheral hardware such as timers and I/O ports
to addresses F80H to FFFH in the data memory space as shown in Fig. 2-1. This means that there is no particular
instruction to control peripheral hardware, but all peripheral hardware is controlled using memory manipu-
lation instructions. (Some mnemonics for hardware control are available to make programs readable.)
To manipulate peripheral hardware, the addressing modes listed in Table 2-3 can be used.
The display data memory, key scan registers, and port H mapped to addresses 1A0H to 1FFH are to be
manipulated by specifying memory bank 1.
Table 2-3 Addressing Modes Applicable to Peripheral Hardware Mapped to Addresses F80H to FFFH
Table 2-4 summarizes the I/O map of the
μ
PD75238.
The items in Table 2-4 have the following meanings:
Symbol:
Name representing the address of incorporated hardware, which can be coded in the operand
field of an instruction
Indicates whether the hardware allows read/write operation.
R/W: Both read and write operations possible
R
: Read only
W
: Write only
Number of manipulatable bits:
Indicates the number of bits that can be processed in hardware manipulation
Bit manipulation addressing:
Bit manipulation addressing applicable in hardware bit manipulation
R/W
:
Bit manipulation
4-bit manipulation
8-bit manipulation
Direct addressing mode specifying mem.bit with MBE = 0 or
(MBE = 1, MBS = 15)
Direct addressing mode specifying fmem.bit regardless of MBE
and MBS setting
Indirect addressing mode specifying pmem.@L regardless of
MBE and MBS setting
Direct addressing mode specifying mem with MBE = 0 or (MBE
= 1, MBS = 15)
Register indirect addressing mode specifying @HL with (MBE
= 1, MBS = 15)
Direct addressing mode specifying mem (even address) with
MBE = 0 or (MBE = 1, MBS = 15)
Register indirect addressing mode specifying @HL (with the L
register containing an even number) with (MBE = 1, MBS = 15)
All hardware allowing bit
manipulation
IST0, IST1, MBE, RBE,
IE
×××
, IRQ
×××
, PORTn.0-3
PORTn.
All hardware allowing 4-bit
manipulation
All hardware allowing 8-bit
manipulation addressing
Applicable addressing mode
Applicable hardware
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