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參數(shù)資料
| 型號： | UPD72850AGK-9EU |
| 廠商： | NEC Corp. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:56; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:25; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:25-4 RoHS Compliant: No |
| 中文描述： | IEEE1394連接400Mbps的物理層 |
| 文件頁數(shù)： | 31/48頁 |
| 文件大?。?/td> | 290K |
| 代理商： | UPD72850AGK-9EU |
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Data Sheet S14452EJ1V0DS00
31
μ
PD72850A
Link controls the interface by generating Idle, Hold or Transmit to CTL0,CTL1, after 1 SCLK cycle when Grant
from PHY is detected.
Assert 1 Idle cycle before asserting Hold and Transmit (do not output 2 or more Idle cycles). When the packet
transmission is not ready, assert Hold. The Hold output period after Grant is detected should not exceed the
period provided by MAX_HOLD.
The following limitations exist though Link can transmit the concatenated packet with a different transfer rate. Link
cannot transmit other than S100 connecting packets after S100 (concatenated) packets have been transmitted. A
new request to transmit must be issued in order to transmit S100 packets at a transfer rate of S200 or more.
If the En_Multi bit in the PHY register is 0, the
μ
PD72850A assumes the same speed as the first packet, for all of
the concatenated packets.
At the end of packet transmission, Link asserts Idle to CTL for a period of 2 cycles.
After sampling Idle from Link, the
μ
PD72850A asserts Idle to CTL for a period of 1 cycle.
4.7 Cancel
This section describes how Link operates, when after the bus has been acquired by the request of LREQ, there is
no data transmission. In this case, a Null packet with no data is transmitted to the serial bus (DATA_PREFIX
→
DATA_END).
Following are two method for canceling the Link:
1. As explained in Section 4.6, the Link outputs Idle or Hold, then outputs Transmit to CTL after confirming Grant.
Here, the Link asserts Idle for two cycles to CTL, then switches to high impedance.
The
μ
PD72850A confirms Cancel at the second Idle cycle. To prevent the bus from switching to high
impedance, a third Idle cycle is needed.
Figure 4-7. Link Cancel Timing (After Grant)
00
11
00
ZZ
ZZ
00
00
00
00
ZZ
ZZ
00
ZZ
ZZ
ZZ
00
00
ZZ
ZZ
ZZ
ZZ
00
00
ZZ
PHY CTL0,CTL1
PHY D0-D7
Link CTL0,CTL1
Link D0-D7
ZZ
ZZ
00
00
2. To cancel after asserting Hold, assert Idle between two cycles; it switches to high impedance. This method
cancels the packet transmission connection (concatenated) after Grant is received. The
μ
PD72850A cancels
with the next Idle cycle of Hold. To prevent CTL from switching to high impedance, assert a second Idle cycle.
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