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參數(shù)資料
| 型號： | UPD72042AGT |
| 廠商： | NEC Corp. |
| 英文描述： | LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL |
| 中文描述： | LSI器件間設(shè)備BusTM（IEBusTM）協(xié)議控制 |
| 文件頁數(shù)： | 43/92頁 |
| 文件大?。?/td> | 541K |
| 代理商： | UPD72042AGT |
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μ
PD72042A, 72042B
43
DATA SHEET S13990EJ2V0DS00
[CEX]
1 : A command is currently being executed.
0 : Execution of a command has terminated. A command code can be set in CMR.
The CEX flag is set and reset as described below.
Set
: When a command code is set in CMR
Reset : When
μ
PD72042A or
μ
PD72042B command processing is terminated
[RAW]
1 : The
μ
PD72042A or
μ
PD72042B is running away.
0 : The
μ
PD72042A or
μ
PD72042B is not running away.
The RAW flag is used to indicate a microprogram crash in the
μ
PD72042A or
μ
PD72042B, as detected by a
watchdog timer.
When the RAW flag is set to 1, a request to interrupt the microcomputer is issued. An interrupt pulse signal is
output on the IRQ pin, and the IRQ flag of the FLG register is set. At this time. The microcomputer must reset the
μ
PD72042A or
μ
PD72042B by driving the RESET pin of the
μ
PD72042A or
μ
PD72042B low or by setting the SRST
flag of the CTR register to 1.
[STM]
1 : Standby mode is set.
0 : Standby mode is not set.
[IRQ]
1 : An interrupt request was made.
0 : No interrupt request is made.
The IRQ flag is set when a return code including the code in the RCR register is changed
Note
, or when the RAW
flag changes from 0 to 1 (crash). When the FLG register is read with the IRQ flag set to 1, the IRQ flag is reset.
For details of the return codes, see the description of the RCR register.
Note
IRQ flag setting depends on the IRS value of the CMR register.
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