參數(shù)資料
型號： UPD72042AGT
廠商： NEC Corp.
英文描述： LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL
中文描述： LSI器件間設備BusTM（IEBusTM）協(xié)議控制
文件頁數(shù)： 33/92頁
文件大?。?/td> 541K
代理商： UPD72042AGT
μ
PD72042A, 72042B
33
DATA SHEET S13990EJ2V0DS00
Cautions 1. In standby mode (with STM of the FLG register set to 1), the user can only write to the CTR
register (including standby mode cancellation) and read from the FLG register.
2. Never access a free address.
3. Slave status (SSR) can be read into RBF by setting the control bits to 0H or 6H from the master
unit.
CTR
Address
Read/write
When reset :
×××
00
××
1B
: 0000B (0H)
: Write
Control register
CTR is a one-byte write register used to control
μ
PD72042A and
μ
PD72042B operations.
b7
—
b6
—
b5
—
b4
b3
b0
—
CTR
b2
b1
REEN
SRST
—
STREQ
[REEN]
When REEN is set to 1, the SLRE flag of the FLG register is immediately set to 1 to enable both slave and broadcast
reception.
[SRST]
When SRST is set to 1, the
μ
PD72042A or
μ
PD72042B is immediately reset. (Note, however, that STREQ is set
to a written value.)
[STREQ]
1: Requests standby mode.
0: Exits from standby mode.
Standby mode setting and cancellation
The
μ
PD72042A or
μ
PD72042B is requested to enter the standby mode by setting the STREQ flag to 1 from the
microcomputer. The
μ
PD72042A or
μ
PD72042B enters standby mode when the standby mode input enabled state
(carrier sense state) is set. In this case, the impedance of the BUS+ and BUS– pins goes high (logic 1), and the
STM flag of the FLG register is set to 1. In standby mode, oscillation is stopped, and all operations are stopped
while preserving the internal data, thus minimizing power consumption.
When, in standby mode, the STREQ flag is set to 0 from the microcomputer, standby mode is cancelled
after the period (about 20 ms at f
X
= 6 MHz) needed for oscillation to stabilize; the halted operations are resumed
from the point at which standby mode was set. At this time, the STM flag of the FLG register changes to 0.
In standby mode, only writing to the CTR register (for standby mode cancellation) and reading from the FLG register
can be performed from the microcomputer.
Cautions 1. When the SRST flag and STREQ flag are simultaneously set to 1, standby mode is set after
software reset. (This state is the same as that set by hardware reset.) Note, however, that
when the SRST flag is set to 1 in standby mode, a software reset is performed, but this is not
reflected in the FLG register.
2. Do not read any data from internal registers via the serial I/O during the period from when a
microcomputer sets the STREQ flag to 1 to when the
μ
PD72042A or
μ
PD72042B enters the
standby mode. This period is one-communication frame at maximum.
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