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參數(shù)資料
| 型號(hào)： | UPD72042AGT |
| 廠商： | NEC Corp. |
| 英文描述： | LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL |
| 中文描述： | LSI器件間設(shè)備BusTM（IEBusTM）協(xié)議控制 |
| 文件頁(yè)數(shù)： | 30/92頁(yè) |
| 文件大?。?/td> | 541K |
| 代理商： | UPD72042AGT |
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μ
PD72042A, 72042B
30
DATA SHEET S13990EJ2V0DS00
3.4 STANDBY MODE SETTING AND CANCELLATION
Standby mode can be set by setting STREQ of the CTR register to 1. The XI pin for oscillation is tied to GND,
and the impedance of the XO pin goes high.
In standby mode (with the STM flag of the FLG register set to 1), only the following registers can be accessed:
Writable register
Readable register
: CTR (address 0000B)
: FLG (address 0001B)
Standby mode can be cancelled by setting STREQ of the CTR register to 0.
Caution Do not read any data from internal registers via the serial I/O during the period from when a
microcomputer sets the STREQ flag to 1 to when the
μ
PD72042A or
μ
PD72042B enters the
standby mode. This period is one-communication frame at maximum.
3.5 RESET MODE SETTING AND CANCELLATION
For hardware reset, the registers are initialized and standby mode is set. (During this period, oscillation is stopped.)
For software reset, the registers are initialized, and operation is started.
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| UPD72042B | LSI DEVICES FOR Inter Equipment BusTM (IEBusTM) PROTOCOL CONTROL |
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