參數(shù)資料
型號： UPD70741GC-25-8EU
廠商： NEC Corp.
元件分類： 16位微控制器
英文描述： V821TM 32-/16-BIT MICROPROCESSOR
中文描述： V821TM 32-/16-BIT微處理器
文件頁數(shù)： 61/112頁
文件大小： 605K
代理商： UPD70741GC-25-8EU
μ
PD70741
61
Table 15-1. Instruction Mnemonics (In Alphabetical Order) (9/9)
Instruction
Operand (s)
Format
CY OV
S
Z
Instruction function
mnemonic
SUBF.S
reg1, reg2
VII
*
0
*
*
Floating-point subtraction:
Subtracts the single-precision floating-point data in
the reg1-specified register from that for reg2, then
stores the result into the reg2-specified register while
changing flags according to the result.
TRAP
vector
II
-
-
-
-
Software trap:
Jumps to a trap handler address according to the
vector-specified trap vector (from 0 to 31) to start an
exception handling after completing all necessary
saving and presetting procedures as follows:
(1) Saving the restore PC and PSW into the FEPC
and FEPSW system registers, respectively, if the
PSW’s EP flag = 1, or into the EIPC and EIPSW
system registers, respectively, if EP = 0
(2) Setting an exception code into the ECR’s FECC
and FEPSW flags if the PSW’s EP flag = 1, or into
the ECR’s EICC if EP = 0
(3) Setting the PSW’s ID flag and clearing the PSW’s
AE flag
(4) Setting the PSW’s NP flag if the PSW’s EP flag
= 1, or setting the PSW’s ID flag if EP = 0
TRNC.SW
reg1, reg2
VII
-
0
*
*
Conversion from floating-point data to integer:
Converts the single-precision floating-point data in the
reg1-specified register into an integer data, then stores
the result into the reg2-specified register while changing
flags according to the result.
XOR
reg1, reg2
I
-
0
*
*
Exclusive OR:
Performs a logical exclusive-OR operation on the
word data in the reg2-specified register and that for
reg1, then stores the result into the reg2-specified
register.
XORBSU
-
II
-
-
-
-
Transfer of exclusive ORed bit string:
Performs a logical exclusive-OR operation on the
source and destination bit strings, then transfers the
result to the destination bit string.
XORI
imm16, reg1, reg2
V
-
0
*
*
Exclusive OR:
Zero-extends the 16-bit immediate data to 32 bits and
performs a logical exclusive-OR operation on the
extended immediate data and the word data in the
reg1-specified register, then stores the result into the
reg2-specified register.
XORNBSU
-
II
-
-
-
-
Transfer after exclusive-ORing a NOTted bit string
and another bit string:
Obtains the 1’s complement (NOT) of the source bit
string, and exclusive-ORs it with the destination bit
string, then transfers the result to the destination bit
string.
相關(guān)PDF資料
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