參數(shù)資料
型號: UPD70741GC-25-8EU
廠商: NEC Corp.
元件分類: 16位微控制器
英文描述: V821TM 32-/16-BIT MICROPROCESSOR
中文描述: V821TM 32-/16-BIT微處理器
文件頁數(shù): 49/112頁
文件大?。?/td> 605K
代理商: UPD70741GC-25-8EU
μ
PD70741
49
14. RESET FUNCTIONS
Inputting a low level to the RESET pin triggers a system reset, thus initializing the on-chip hardware.
When the RESET pin is driven from a low level to a high, the CPU starts program execution. The registers should
be initialized in a program as required.
14.1
Features
The reset pin is provided with a noise suppressor circuit based on an analog delay (60 to 300 ns).
14.2
Pin Functions
Table 14-1 lists the state of the output from each pin during a system reset. The output state is retained during
the entire reset period.
After the RESET pin is kept at a low level for 30 clock cycles, if the HLDRQ signal is inactive, a memory read cycle
is started to fetch an instruction.
Even during a reset period (when the RESET pin is kept at a low level), activating the HLDRQ signal can place
the bus on hold. The state of each pin with the bus put on hold during a reset is basically the same as that with the
bus put on hold during a non-reset period.
The HLDRQ signal should be kept inactive during a power-on reset.
It is necessary to provide a pull-up or pull-down resistor to the pins that become high impedance during a reset.
If no pull-up or pull-down resistor is provided to these pins, memory may be damaged when the pins are driven to
high impedance.
The CLKOUT pin supplies clock pulses even during a reset.
Table 14-1. Output State of Each Pin during a Reset
Pin
Operation state
Pin
Operation state
A0-A23
Not defined
HLDAK
High level
D0-D15
High impedance
MRD
P00/TCLR
LMWR/WE
P01/DREQ0
UMWR
P02/DACK0
IORD
P03/DREQ1
IOWR
P04/DACK1
CS1-CS3
P05/SI
RAS
P06/SO
LCAS
P07/SCLK
UCAS
P08/TXD/UBE
CS0/REFRQ
P09/RXD/TC
BLOCK/WDTOUT
Low level
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