參數(shù)資料
型號(hào): UPD70741GC-25-8EU
廠商: NEC Corp.
元件分類: 16位微控制器
英文描述: V821TM 32-/16-BIT MICROPROCESSOR
中文描述: V821TM 32-/16-BIT微處理器
文件頁數(shù): 19/112頁
文件大?。?/td> 605K
代理商: UPD70741GC-25-8EU
μ
PD70741
19
3.3.2 System register set
System registers are used to control the state of the CPU and store interrupt information.
Table 3-2. System Register Numbers
No.
Register name
Use
Explanation
0
EIPC
Registers for saving the current
status upon the occurrence of an
exception or interrupt
Retain the contents of PC and PSW if an exception or
interrupt occurs. Note, however, that there is only one
pair of these registers.
When multiple interrupts are allowed, therefore, the
contents of the registers must be saved by the program.
1
EIPSW
2
FEPC
Registers for saving the current
status upon the occurrence of an
NMI or double exception
Retain the contents of PC and PSW if an
NMI or double exception occurs.
3
FEPSW
4
ECR
Exception source register
Stores the source of an exception, maskable interrupt, or
NMI. The upper 16 bits of this register are called
"FECC" and set to the exception code of an NMI/double
exception. The lower 16 bits are called "EICC" and set
to the exception code of an exception/interrupt.
5
PSW
Program status word
The program status word is a set of flags indicating the
state of the program (result of executing an instruction)
and the state of the CPU.
6
PIR
Processor ID register
Used to identify a CPU type number.
7
TKCW
Task control word
Used to control a floating-point operation.
8-23
Reserved
24
CHCW
Cache control word
Used to control the built-in instruction cache.
25
ADTRE
Address trap register
Stores the address used to detect an address match with
PC, and to generate an address trap.
26-31
Reserved
Read and write operations made to these system registers can be performed using the system register load/store
instructions (LDSR and STSR) with the system register numbers specified.
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