參數(shù)資料
型號(hào)： UPD70741GC-25-8EU
廠商： NEC Corp.
元件分類： 16位微控制器
英文描述： V821TM 32-/16-BIT MICROPROCESSOR
中文描述： V821TM 32-/16-BIT微處理器
文件頁數(shù)： 28/112頁
文件大小： 605K
代理商： UPD70741GC-25-8EU
μ
PD70741
28
Table 4-1. Interrupts (1/2)
Type
Category
Group Priority
Interrupt/exception source
Exception
Handler
Return
in group
Name
Source
Unit
code
address
PC
Note 1
Reset
Interrupt
-
-
RESET
Reset input
-
FFF0H
FFFFFFF0H
Undefined
Non-
maskable
Interrupt
-
-
NMI
NMI input
-
FFD0H
FFFFFFD0H
Next
PC
Note 2
Software
Exception
-
-
TRAP1nH
trap instruction
-
FFBnH
FFFFFFB0H
Next PC
exception
-
-
TRAP0nH
trap instruction
-
FFAnH
FFFFFFA0H
Next PC
Exception Exception
-
-
DP-EX
Double exception
-
Note 3
FFFFFFD0H
Current
trap
-
-
AD-TR
Address trap
-
FFC0H
FFFFFFC0H
PC
-
-
I-OPC
Invalid instruction
code
-
FF90H
FFFFFF90H
-
-
DIV0
Division by zero
-
FF80H
FFFFFF80H
-
-
FIZ
Invalid floating-
point operation
-
FF70H
FFFFFF60H
-
-
FZD
Floating-point
division by zero
-
FF68H
FFFFFF60H
-
-
FOV
Floating-point
overflow
-
FF64H
FFFFFF60H
-
-
FUD
Floating-point
underflow
Note 4
-
FF62H
FFFFFF60H
-
-
FPR
Floating-point
degraded
precision
Note 4
-
FF61H
FFFFFF60H
-
-
FRO
Floating-point
reserved operand
-
FF60H
FFFFFF60H
Remark
n = 0H to FH
Notes 1.
PC value saved in EIPC or FEPC at the beginning of interrupt/exception handling
2.
Return PC = current PC if an interrupt occurred during the execution of an instruction which was stopped
by an interrupt (DIV/DIVU, floating-point, and bit string instructions).
3.
The exception code for the exception which occurred first is written into in the 16 low-order bits of ECR,
while and that for the second exception is written into the 16 high-order bits.
4.
The V821 is not subject to floating-point underflow or degraded precision exceptions.
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