
Preliminary Data Sheet U14168EJ2V0DS00
65
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(6/7)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY
OV
S
Z
SAT
rr r r r 1 0 0 1 d d d d d dd
SST.H
reg2,disp8[ep]
Note 19
adr
←
ep+zero-extend(disp8)
Store-memory(adr,GR[reg2],Half-word)
1
1
1
rr r r r 1 0 1 0 d d d d d d1
SST.W
reg2,disp8[ep]
Note 21
adr
←
ep+zero-extend(disp8)
Store-memory(adr,GR[reg2],Word)
1
1
1
rr r r r 1 1 1 0 1 0 R R R RR
ST.B
reg2,disp16[reg1]
dd d d d d d d d d d d d d dd
adr
←
GR[reg1]+sign-extend(disp16)
Store-memory(adr,GR[reg2],Byte)
1
1
1
rr r r r 1 1 1 0 1 1 R R R RR
dd d d d d d d d d d d d d d0
ST.H
reg2,disp16[reg1]
Note 8
adr
←
GR[reg1]+sign-extend(disp16)
Store-memory(adr,GR[reg2],Half-word)
1
1
1
rr r r r 1 1 1 0 1 1 R R R RR
dd d d d d d d d d d d d d d1
ST.W
reg2,disp16[reg1]
Note 8
adr
←
GR[reg1]+sign-extend(disp16)
Store-memory(adr,GR[reg2],Word)
1
1
1
rr r r r 1 1 1 1 1 1 R R R RR
STSR
regID,reg2
00 0 0 0 0 0 0 0 1 0 0 0 0 00
GR[reg2]
←
SR[regID]
1
1
1
SUB
reg1,reg2
rr r r r 0 0 1 1 0 1 R R R RR
GR[reg2]
←
GR[reg2]
GR[reg1]
1
1
1
×
×
×
×
SUBR
reg1,reg2
rr r r r 0 0 1 1 0 0 R R R RR
GR[reg2]
←
GR[reg1]
GR[reg2]
1
1
1
×
×
×
×
SWITCH
reg1
00 0 0 0 0 0 0 0 1 0 R R R RR
adr
←
(PC+2)+(GR[reg1] logically shift left
by 1)
PC
←
(PC+2)+(sign-extend(Load-
memory(adr,Half-word)))
logically shift left by 1
5
5
5
SXB
reg1
00 0 0 0 0 0 0 1 0 1 R R R RR
GR[reg1]
←
sign-extend
(GR[reg1] (7 : 0)
1
1
1
SXH
reg1
00 0 0 0 0 0 0 1 1 1 R R R RR
GR[reg1]
←
sign-extend
(GR[reg1] (15 : 0))
1
1
1
00 0 0 0 1 1 1 1 1 1 i i i ii
TRAP
vector
00 0 0 0 0 0 1 0 0 0 0 0 0 00
EIPC
←
PC+4 (restore PC)
←
PSW
←
Interrupt code
←
1
←
1
←
00000040H (when vector
is 00H to 0FH)
EIPSW
ECR.EICC
PSW.EP
PSW.ID
PC
00000050H (when vector
is 10H to 1FH)
3
3
3
TST
reg1,reg2
rr r r r 0 0 1 0 1 1 R R R RR
result
←
GR[reg2] AND GR[reg1]
1
1
1
0
×
×
11 b b b 1 1 1 1 1 0 R R R RR
bit#3,disp16[reg1]
dd d d d d d d d d d d d d dd
adr
←
GR[reg1]+sign-extend(disp16)
Z flag
←
Not(Load-memory-bit(adr,bit#3))
3
Note 3
3
Note 3
3
Note 3
×
rr r r r 1 1 1 1 1 1 R R R RR
TST1
reg2,[reg1]
00 0 0 0 0 0 0 1 1 1 0 0 1 10
adr
←
GR[reg1]
Z flag
←
Not(Load-memory-bit(adr,reg2))
3
Note 3
3
Note 3
3
Note 3
×