參數(shù)資料
型號: UPD703100-33
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁數(shù): 15/132頁
文件大?。?/td> 1174K
代理商: UPD703100-33
Preliminary Data Sheet U14168EJ2V0DS00
15
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(2/4)
Pin Name
I/O
Function
Alternate Function
INTP130
P34
INTP131
P35/SO2
INTP132
P36/SI2
INTP133
I
External maskable interrupt request input, also used as external capture
trigger input for timer 13
P37/SCK2
INTP140
P114
INTP141
P115/SO3
INTP142
P116/SI3
INTP143
I
External maskable interrupt request input, also used as external capture
trigger input for timer 14
P117/SCK3
INTP150
P124
INTP151
P125
INTP152
P126
INTP153
I
External maskable interrupt request input, also used as external capture
trigger input for timer 15
P127/ADTRG
SO0
P22/TXD0
SO1
P25/TXD1
SO2
P35/INTP131
SO3
O
Serial transmit data output (3-wire) for CSI0 to CSI3
P115/INTP141
SI0
P23/RXD0
SI1
P26/RXD1
SI2
P36/INTP132
SI3
I
Serial receive data input (3-wire) for CSI0 to CSI3
P116/INTP142
SCK0
P24
SCK1
P27
SCK2
P37/INTP133
SCK3
I/O
Serial clock I/O (3-wire) for CSI0 to CSI3
P117/INTP143
TXD0
P22/SO0
TXD1
O
Serial transmit data output for UART0 and UART1
P25/SO1
RXD0
P23/SI0
RXD1
I
Serial receive data input for UART0 and UART1
P26/SI1
D0 to D7
P40 to P47
D8 to D15
I/O
16-bit data bus for external memory
P50 to P57
A0 to A7
PA0 to PA7
A8 to A15
PB0 to PB7
A16 to A23
O
24-bit address bus for external memory
P60 to P67
LWR
O
Lower byte write-enable signal output for external data bus
P90/LCAS
UWR
O
Higher byte write-enable signal output for external data bus
P91/UCAS
RD
O
Read strobe signal output for external data bus
P92
WE
O
Write enable signal output for DRAM
P93
OE
O
Output enable signal output for DRAM
P95
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