參數資料
型號: UPD703100-33
廠商: NEC Corp.
英文描述: V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: V850E/MS1TM 32/16單晶片微控制器
文件頁數: 16/132頁
文件大?。?/td> 1174K
代理商: UPD703100-33
Preliminary Data Sheet U14168EJ2V0DS00
16
μ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33
(3/4)
Pin Name
I/O
Function
Alternate Function
LCAS
O
Column address strobe signal output for DRAM’s lower data
P90/LWR
UCAS
O
Column address strobe signal output for DRAM’s higher data
P91/UWR
RAS0 to RAS3
P80/CS0 to P83/CS3
RAS4
P84/CS4/IOWR
RAS5
P85/CS5/IORD
RAS6
P86/CS6
RAS7
O
Low address strobe signal output for DRAM
P87/CS7
BCYST
O
Strobe signal output indicating start of bus cycle
P94
CS0 to CS3
P80/RAS0 to
P83/RAS3
CS4
P84/RAS4/IOWR
CS5
P85/RAS5/IORD
CS6
P86/RAS6
CS7
O
Chip select signal output
P87/RAS7
WAIT
I
Control signal input for inserting waits in bus cycle
PX6
REFRQ
O
Refresh request signal output for DRAM
PX5
IOWR
O
DMA write strobe signal output
P84/RAS4/CS4
IORD
O
DMA read strobe signal output
P85/RAS5/CS5
DMARQ0 to
DMARQ3
I
DMA request signal input
P04/INTP100 to
P07/INTP103
DMAAK0 to
DMAAK3
O
DMA acknowledge signal output
P14/INTP110 to
P17/INTP113
TC0 to TC3
O
DMA end (terminal count) signal output
P104/INTP120 to
P107/INTP123
HLDAK
O
Bus hold acknowledge output
P96
HLDRQ
I
Bus hold request input
P97
ANI0 to ANI7
I
Analog input to A/D converter
P70 to P77
NMI
I
Non-maskable interrupt request input
P20
CLKOUT
O
System clock output
PX7
CKSEL
I
Input for specifying clock generator’s operation mode
MODE0 to
MODE3
I
Specify operation modes
RESET
I
System reset input
X1
I
X2
Oscillator connection for system clock. Input is via X1 when using an
external clock.
ADTRG
I
A/D converter external trigger input
P127/INTP153
AV
REF
I
Reference voltage input for A/D converter
AV
DD
Positive power supply for A/D converter
AV
SS
Ground potential for A/D converter
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