參數(shù)資料
型號： UPD68AMC-XXX-5A4
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 4.5 MHz, MICROCONTROLLER, PDSO20
封裝： 0.300 INCH, PLASTIC, SSOP-20
文件頁數(shù)： 3/73頁
文件大?。?/td> 561K
代理商： UPD68AMC-XXX-5A4
9
PD67, 67A, 68, 68A, 69
Data Sheet U14935EJ2V1DS
2. INTERNAL CPU FUNCTIONS
2.1 Program Counter (PC): 11 Bits (
PD67, 67A, 68, 68A)
12 Bits (
PD69)
The program counter (PC) is a binary counter that holds the address information of the program memory.
Figure 2-1. Program Counter Configuration
The PC contains the address of the instruction that should be executed next.
Normally, the counter contents
are automatically incremented in accordance with the instruction length (byte count) each time an instruction is
executed.
However, when executing jump instructions (JMP, JC, JNC, JF, JNF), the PC contains the jump destination
address written in the operand.
When executing the subroutine call instruction (CALL), the call destination address written in the operand is
entered in the PC after the PC contents at the time are saved in the address stack register (ASR).
If the return
instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to
the PC.
After reset, the value of the PC becomes “000H”.
2.2 Stack Pointer (SP): 1 Bit
This is a 1-bit register that holds the status of the address stack register.
The stack pointer contents are incremented when the call instruction (CALL) is executed and decremented when
the return instruction (RET) is executed.
When reset, the stack pointer contents are cleared to 0.
When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is defined as hung up, a system
reset signal is generated, and the PC becomes 000H.
As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer
by means of a program.
2.3 Address Stack Register (ASR (RF)): 11 Bits (
PD67, 67A, 68, 68A)
12 Bits (
PD69)
The address stack register saves the return address of the program after a subroutine call instruction is executed.
The lower 8 bits are allocated in RF of the data memory as a alternate-function RAM.
The register holds the
ASR value even after the RET instruction is executed.
After reset, it holds the previous data (undefined when turning on the power).
Caution If RF is accessed as the data memory, the higher 3 bits of the
PD67, 67A, 68, and 68A, and
higher 4 bits of the
PD69 become undefined.
Figure 2-2.
Address Stack Register Configuration
PC9
PC10
PC0
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PD67, 67A, 68, 68A
PC11
PD69
PC
ASR10
ASR9
ASR8
ASR7
ASR6
ASR5
ASR4
ASR3
ASR2
ASR1
ASR0
ASR
RF
PD69
ASR11
PD67, 67A, 68, 68A
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