參數(shù)資料
型號: UPD68AMC-XXX-5A4
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 4.5 MHz, MICROCONTROLLER, PDSO20
封裝: 0.300 INCH, PLASTIC, SSOP-20
文件頁數(shù): 10/73頁
文件大?。?/td> 561K
代理商: UPD68AMC-XXX-5A4
16
PD67, 67A, 68, 68A, 69
Data Sheet U14935EJ2V1DS
3.2.2 S0 port (bit 2 of P1)
The S0 port is an input/OFF mode port.
The pin state can be read by setting this port to input mode using bit 0 of the P4 register.
In input mode, the use of a pull-down resistor for the S0 and S1/LED port can be specified in 2-bit units by software
using bit 4 of the P4 register.
If input mode is released (thus set to OFF mode), the pin becomes high-impedance but is configured so that
through current does not flow internally. In OFF mode, 1 can be read regardless of the pin state.
After reset, S0 is set to OFF mode, thus becoming high-impedance.
3.2.3 S1/LED port (bit 3 of P1)
The S1/LED port is an I/O port.
Input or output mode can be set using bit 2 of the P4 resister. The pin state can be read in both input mode
and output mode.
When in input mode, the use of a pull-down resistor for the S0 and S1/LED ports can be specified in 2-bit units
by software using bit 4 of the P4 register.
When in output mode, the pull-down resistor is automatically disconnected and this pin becomes the remote
control transmission display pin (refer to 4 TIMER).
After reset, S1/LED is placed in output mode, and a high level is output.
3.2.4 S2 port (bit 1 of P1)
The S2 port is an input port.
Use of STOP mode release for the S2 port can be specified by bit 3 of the P4 register.
When using the pin as a key input from a key matrix, enable (bit 3 of the P4 register is set to 1) the use of STOP
mode release (at this time, a pull-down resistor is connected internally.) When STOP mode release is disabled
(bit 3 of the P4 register is set to 0), it can be used as an input port that does not release the STOP mode even if
the release condition is met (at this time, a pull-down resistor is not connected internally.)
The state of the pin can be read in both cases.
After reset, S2 is set to input mode where the STOP mode release is disabled, and enters a high-impedance
state.
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