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參數資料
| 型號： | UPD68AMC-XXX-5A4 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 4.5 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, SSOP-20 |
| 文件頁數： | 25/73頁 |
| 文件大小： | 561K |
| 代理商： | UPD68AMC-XXX-5A4 |
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29
PD67, 67A, 68, 68A, 69
Data Sheet U14935EJ2V1DS
Table 5-3. Standby Mode Setup (HALT #b3b2b1b0B) and Release Conditions
Operand Value of
HALT Instruction
Setting Mode
Precondition for Setup
Release Condition
b3
b2
b1
b0
0000
STOP
All KI/O pins are high-level output.
High level is input to at least one
of KI pins.
011
STOP
All KI/O pins are high-level output.
High level is input to at least one
of KI pins.
110
STOPNote 1
The KI/O0 pin is high-level output.
High level is input to at least one
of KI pins.
1
Any of the
STOP
[The following condition is added in addition to the above.]
combinations of
—
High level is input to at least one
b2b1b0 above
of S0, S1 and S2 pinsNote 2.
0/1
101
HALT
—
When the timer’s down counter is 0
Notes 1. When setting HALT #
×110B, configure a key matrix by using the KI/O0 pin and the KI pin so that the
standby mode can be released.
2. At least one of the S0, S1 and S2 pins (the pin used for releasing the standby mode) must be specified
as follows:
S0, S1 pins:
Input mode (specified by bits 0 and 2 of the P4 register)
S2 pin:
Use of STOP mode release enabled (specified by bit 3 of the P4 register)
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value
other than that above or when the precondition has not been satisfied when executing the
HALT instruction.
2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system
is placed in STOP mode only after all the 10 bits of the timer’s down counter and the timer
output permit flag are cleared to 0.
3. Write the NOP instruction as the first instruction after STOP mode is released.
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