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| 型號(hào)： | UPD68AMC-XXX-5A4 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, OTPROM, 4.5 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, SSOP-20 |
| 文件頁(yè)數(shù)： | 27/73頁(yè) |
| 文件大?。?/td> | 561K |
| 代理商： | UPD68AMC-XXX-5A4 |
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31
PD67, 67A, 68, 68A, 69
Data Sheet U14935EJ2V1DS
6. RESET
A system reset is effected by the following causes:
When the POC circuit has detected low power-supply voltage
When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed
When the accumulator is 0H when the RLZ instruction is executed
When stack pointer overflows or underflows
Table 6-1. Hardware Statuses After Reset
Hardware
Reset by On-Chip POC Circuit During Operation
Reset by the On-Chip POC Circuit During
Reset by Other FactorsNote 1
Standby Mode
PC 11 bits:
PD67, 67A, 000H
68, 68A
12 bits:
PD69
SP (1 bit)
0B
Data
R0 = DP
000H
memory
R1 to RF
Undefined
Accumulator (A)
Undefined
Status flag (F)
0B
Carry flag (CY)
0B
Timer (10 bits)
000H
Port register
P0
FFH
P1
×××× 11×1BNote 2
Control register P3
0000
×000BNote 3
P4
26H
Notes 1. The following resets are available.
Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy
the precondition)
Reset when executing the RLZ instruction (when A = 0)
Reset by stack pointer’s overflow or underflow
2.
×: Refers to the value by the KI or S2 pin status.
In order to prevent malfunction, be sure to input a low level to one or more of pins KI0 to KI3 when
POC is released by supply voltage rising (Can be left open. When open, leave the pull-down resistor
connected).
3.
×: Refers to the value based on a decrease of power supply voltage (0 when VDD ≤ VID).
Remark VID: RAM retention detection voltage
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| UPD68MC-XXX-5A4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROCONTROLLER|4-BIT|CMOS|SSOP|20PIN|PLASTIC |
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