參數(shù)資料
型號: UPB1009K-E1
廠商: NEC Corp.
英文描述: NECs LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT
中文描述: 鄰舍低功耗GPS射頻接收器雙極模擬集成電路
文件頁數(shù): 14/27頁
文件大小: 344K
代理商: UPB1009K-E1
ELECTRICAL CHARACTERISTICS (T
A
= +25
°
C, V
CC
= 3.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
<PLL Synthesizer>
Circuit Current 4
I
CC4
PLL, VCO current, MS1 = L, MS2 = L
8.0
9.5
10.6
mA
I
cpsink
0.55
0.45
0.35
mA
Charge Pump Output Current
I
cpsource
V
13 pin
= V
CC
/2
0.35
0.45
0.55
mA
Loop Filer Output (High Level)
V
OH
V
CC
0.3
V
Loop Filer Output (Low Level)
V
OL
0.2
V
Reference Input Level
V
REFin
0.2
1.6
V
PP
VCO Modulation Sensitivity
KV
Center frequency
100
MHz
VCO Control Voltage
VT
When PLL is Locked
0.5
1.3
2.0
V
C/N
C/N
10 kHz
70.0
81.0
dBc/Hz
<A/D Converter>
Circuit Current 5
I
CC5
3.1
4.1
5.4
mA
Resolution
ResAD
4
bits
Sampling Clock
fs
20
MHz
Input Band Width
ADBW
5.1
MHz
Integral Non-linear Error
INL
DC characteristics
0.2
1.0
LSB
Signal-to-noise Ratio
SNR
IF = 5.17 MHz, fs = 20.48 MHz
22.0
25.3
dB
Signal-to-noise + Distortion Ratio
SINAD
IF = 5.17 MHz, fs = 20.48 MHz
20.0
25.1
dB
Number
ENOB
ENOB = (SINAD
1.763)/6.02
3.0
3.9
bits
Total Harmonic Distortion Ratio
THD
IF = 5.17 MHz, fs = 20.48 MHz
Second-degree to fifth-degree distortion
components
40
30
dBc
Remarks 1.
Timing characteristics of ADC during normal operation
A buffer amplifier is internally inserted before the ADC core of the
μ
PB1009K. The bias of this buffer amplifier
is controlled by the signal input from the DC trim pin, and is used to eliminate the DC offset of the ADC.
Because the ladder resistor of the ADC is directly connected between V
DD
ana and GNDana, changes in
V
DD
ana affect the resolution of the ADC.
14
UPB1009K
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