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參數(shù)資料
| 型號： | UPB1009K-E1 |
| 廠商： | NEC Corp. |
| 英文描述： | NECs LOW POWER GPS RF RECEIVER BIPOLAR ANALOG + INTEGRATED CIRCUIT |
| 中文描述： | 鄰舍低功耗GPS射頻接收器雙極模擬集成電路 |
| 文件頁數(shù)： | 12/27頁 |
| 文件大?。?/td> | 344K |
| 代理商： | UPB1009K-E1 |
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ELECTRICAL CHARACTERISTICS (T
A
= +25
°
C, V
CC
= 3.0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Rest current of overall IC in each
mode
Sleep mode
Note
Rest status without input signal, including sampling clock.
MS1 = L, MS2 = L
I
s
PD1 = L, PD2 = L
1.3
2.2
3.5
mA
Warm-up mode
I
w
PD1 = H, PD2 = L
10.5
13.0
15.5
mA
Calibration mode
I
c
PD1 = H, PD2 = H
18.0
22.0
25.3
mA
Active mode
I
a
PD1 = L, PD2 = H
22.1
26.0
30.0
mA
Rest current of PLL block in each
clock mode
Current of PLL block. Overall current in calibration mode and active mode increases from that
in basic mode (MS1 = L, MS2 = L). PD1 = H, PD2 = L.
Current when 1/100 divider is
used
I
w1
MS1 = L, MS2 = L
5.3
6.5
7.6
mA
Current when 256/3 divider is
used
I
w2
MS1 = L, MS2 = H
9.7
11.3
12.6
mA
Current when 1024/9 divider is
used
I
w3
MS1 = H, MS2 = L
10.2
12.1
13.5
mA
Current when 4096/65 divider is
used
I
w4
MS1 = H, MS2 = H
10.4
12.3
13.9
mA
Maximum mode control pin current
H application
20
μ
A
6 pin
MS1
L application
20
μ
A
H application
20
μ
A
12 pin
MS2
L application
20
μ
A
H application
1
μ
A
36 pin
PD1
L application
1
μ
A
H application
1
μ
A
37 pin
PD2
L application
1
μ
A
<Pre-amplifier>
f
RFin
= 1 575.42 MHz
Circuit Current 1
I
CC1
No Signals, 1-pin current
1.9
2.3
2.7
mA
Power Gain
G
LNA
P
RFin
=
40 dBm
12.5
15.0
17.5
dB
Noise Figure
NF
LNA
f
RFin
= 1 575 MHz
3.0
3.5
dB
Saturated Output Power
P
O(SAT)LNA
P
RFin
=
10 dBm
4.0
2.7
dBm
Input 1dB Compression Level
P
LNA
1
f
RFin
= 1 575.42 MHz
25
21.8
dBm
Input 3rd Order Intercept Point
IIP
3LNA
f
RFin
= 1 575.42 MHz, 1 576.42 MHz
12
9.5
dBm
Input Inpedance
Z
inLNA
11.2
j21.5
Output Inpedance
Z
outLNA
Calculated from S-parameter where input
DC cut capacitance = 1 nF, output load L
= 100 n, and DC cut capacitance = 1 nF
16.4
j136.6
Note
Most of the current flows into the ADC ladder resistor (V
DD
ana
→
GNDana) in the sleep mode, and the sleep mode
current between other V
CC
(V
DD
) and GND is 10
μ
A maximum.
12
UPB1009K
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPB1009K-E1-A | 功能描述:射頻接收器 GPS Receiver RoHS:否 制造商:Skyworks Solutions, Inc. 類型:GPS Receiver 封裝 / 箱體:QFN-24 工作頻率:4.092 MHz 工作電源電壓:3.3 V 封裝:Reel |
| UPB100A484B-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| UPB100A484B-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| UPB100A484D-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
| UPB100A484D-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SRAM |
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