參數(shù)資料
型號(hào)： UDA1352HL
廠(chǎng)商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： 48 kHz IEC 60958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁(yè)數(shù)： 42/64頁(yè)
文件大?。?/td> 262K
代理商： UDA1352HL
2003 Mar 25
42
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
12.10 Supplemental settings (write)
Table 48
Register address 40H
Table 49
Description of register bits
BIT
15
14
13
12
11
10
9
8
Symbol
OSCOUT_
EN
0
EV2
Default
0
0
0
0
0
0
0
BIT
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Symbol
Default
BIT
SYMBOL
DESCRIPTION
15
OSCOUT_EN
Crystal oscillator output control.
A 1-bit value to enable the crystal oscillator
output from pin OSCOUT when the crystal oscillator is enabled (bit PON_XTAL
is logic 1 in register address 03H). When set to logic 0, pin OSCOUT is
disabled. When bits OSCOUT_EN and PON_XTAL are both set to logic 1, the
crystal oscillator output appears at pin OSCOUT. Default value 0.
When writing new settings via the L3-bus or I
2
C-bus interfaces, these bits
should stay at logic 0 (default value) to guarantee correct operation.
Pll pull-in range selection.
A 1-bit value to adjust the PLL pull-in range.
When in frequency synthesizer mode (mode 8), this bit should be set to logic 1
to guarantee correct operation. Default value 0.
14 to 11,
9 to 0
10
EV2
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