參數資料
型號: UDA1352HL
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: 48 kHz IEC 60958 audio DAC
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數: 30/64頁
文件大?。?/td> 262K
代理商: UDA1352HL
2003 Mar 25
30
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
11.4
Timing characteristics
11.4.1
F
REQUENCY REQUIREMENTS
The SPDIF specification IEC 60958 supports the following
three levels of clock accuracy:
Level I: High accuracy; requires the transmitted
sampling frequency to have a tolerance of within
50
×
10
6
Level II: Normal accuracy; requires all receivers to have
an input sampling frequency of within 1000
×
10
6
of the
nominal sampling frequency
Level III: Variable pitch shifted clock mode; allows a
sampling frequency deviation of 12.5% of the nominal
sampling frequency.
11.4.2
R
ISE AND FALL TIMES
Rise and fall times (see Fig.16) are defined as:
Rise time =
Fall time =
Rise and fall times should be in the range:
0% to 20% when the data bit is a logic 1
0% to 10% when two consecutive data bits are both
logic 0.
11.4.3
D
UTY CYCLE
The duty cycle (see Fig.16) is defined as:
Duty cycle =
The duty cycle should be in the range:
40% to 60% when the data bit is a logic 1
45% to 55% when two consecutive data bits are both
logic 0.
t
+
t
L
t
H
)
--------------------
100%
×
t
+
t
L
t
H
)
--------------------
100%
×
t
+
t
L
t
H
(
)
--------------------
100%
×
handbook, halfpage
90%
tH
50%
10%
MGU612
tr
tf
tL
Fig.16 Rise and fall times.
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