參數(shù)資料
型號(hào)： UDA1352HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： 48 kHz IEC 60958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁(yè)數(shù)： 3/64頁(yè)
文件大?。?/td> 262K
代理商： UDA1352HL
2003 Mar 25
3
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
1
FEATURES
1.1
General
2.7 to 3.6 V power supply
Integrated digital filter and Digital-to-Analog
Converter (DAC)
256f
s
system clock output
20-bit data path in interpolator
High performance
No analog post filtering required for DAC
Supported sampling frequencies of 28 up to 55 kHz.
1.2
Control
Controlled by either static pins, I
2
C-bus or L3-bus
microcontroller interfaces.
1.3
IEC 60958 input
On-chip amplifier converts IEC 60958 input to CMOS
levels
Lock status indication at pin LOCK
Pulse Code Modulation (PCM) input signal status
indication at pin PCMDET
Right and left channels each have 40 key
channel-status bits available via L3-bus or I
2
C-bus
interfaces.
1.4
Digital sound processing and DAC
Automatic de-emphasis when using IEC 60958 input
with audio sample frequencies (f
s
) of 32.0, 44.1 and
48.0 kHz
Soft mute using a cosine roll-off circuit selectable via
pin MUTE, L3-bus or I
2
C-bus interfaces
Left and right independent dB linear volume control
having 0.25 dB steps from 0 to
50 dB, 1 dB steps to
60,
66 and
∞
dB
Bass boost and treble control in L3-bus or I
2
C-bus
modes
Interpolating filter (f
s
to 64f
s
or 128f
s
) using cascaded
recursive and FIR filters
Fifth-order noise shaper (operating either at 64f
s
or 128f
s
) generates the bitstream for the DAC
Filter Stream DAC (FSDAC).
2
APPLICATIONS
Digital audio systems.
3
GENERAL DESCRIPTION
The UDA1352HL is a single-chip IEC 60958 audio
decoder with an integrated stereo DAC employing
bitstream conversion techniques.
A lock status signal is available on pin LOCK, to indicate
when the IEC 60958 decoder is locked. A PCM detection
status signal is available on pin PCMDET to indicate when
PCM data is present at the input.
By default, the DAC output and the data output interface
are muted when the decoder is out-of-lock. However, this
setting can be overridden in the L3-bus or I
2
C-bus modes.
The UDA1352HL in package LQFP48 is the full featured
version. Also available is the UDA1352TS in package
SSOP28 which has the IEC 60958 input only to the DAC.
4
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
UDA1352HL
LQFP48
plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm
SOT313-2
相關(guān)PDF資料
PDF描述
UDA1360 Low-voltage low-power stereo audio ADC
UDA1360TS Low-voltage low-power stereo audio ADC
UDA1361 96 kHz sampling 24-bit stereo audio ADC
UDA1380 Stereo audio coder-decoder for MD, CD and MP3
UDA1380TT Stereo audio coder-decoder for MD, CD and MP3
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