參數(shù)資料
型號： UDA1352HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： 48 kHz IEC 60958 audio DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48
文件頁數(shù)： 18/64頁
文件大小： 262K
代理商： UDA1352HL
2003 Mar 25
18
Philips Semiconductors
Preliminary specification
48 kHz IEC 60958 audio DAC
UDA1352HL
9
L3-BUS DESCRIPTION
9.1
General
The UDA1352HL has an L3-bus microcontroller interface
allowing all the digital sound processing features and
various system settings to be controlled by a
microcontroller.
The controllable settings are:
Restoring of L3-bus default values
Power-on
Selection of filter mode, and settings for treble and bass
boost
Volume settings for left and right channels
Selection of soft mute via cosine roll-off and bypass of
auto mute
Selection of de-emphasis (mode 4 to mode 8 only).
The readable settings are:
Mute status of interpolator
PLL locked
SPDIF input signal locked
Audio sample frequency
Valid PCM data detected
Pre-emphasis of the IEC 60958 input signal
Clock accuracy.
The exchange of data and control information between the
microcontroller and the UDA1352HL is LSB first and is
accomplished through the serial hardware L3-bus
interface comprising the following pins:
L3DATA: data line
L3MODE: mode line
L3CLOCK: clock line.
The L3-bus format has two modes of operation:
Address mode
Data transfer mode.
The address mode is used to select a device for a
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.6).
The data transfer mode is characterized by L3MODE
being HIGH and is used to transfer one or more bytes
representing a register address, instruction or data.
There are two types of data transfers:
Write action: data transfer to the device
Read action: data transfer from the device.
Remark:
when the device is powered-up, the L3-bus
interface must receive at least one L3CLOCK pulse before
data can be sent to the device (see Fig.6). This is only
required once after the device is powered-up.
9.2
Device addressing
The device address is one byte comprising:
Data Operating Mode (DOM) bits 0 and 1 specifying the
type of data transfer (see Table 6)
Address bits 2 to 7 specifying a 6-bit device address.
Bits 2 and 3 of the address are selected via external
pins DA0 and DA1, allowing up to four UDA1352HL
devices to be independently controlled in a single
application.
The primary address of the UDA1352HL is ‘001000’ (LSB
to MSB) and the default address is ‘011000’.
Table 6
Selection of data transfer
9.3
Register addressing
The device register address is one byte comprising:
Bit 0 specifying that data is to be either read or written
Address bits 1 to 7 specifying the 7-bit register address.
There are three types of register addressing:
To write data: bit 0 is logic 0 specifying that data will be
written to the device register, followed by bits 1 to 7
specifying the device register address (see Fig.6)
To prepare read: bit 0 is logic 1, specifying that data will
be read from the device register (see Fig.7)
To read data: the device returns the device register
address prior to sending data from that register. When
bit 0 is logic 0, the register address is valid; when bit 0 is
logic 1, the register address is invalid.
DOM
TRANSFER
BIT 0
BIT 1
0
1
0
1
0
0
1
1
not used
not used
write data or prepare read
read data
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